343     bool isReg() const { return Kind == CV_Register; }  in isReg()  function in __anoncd4cffa40111::CountValue
347       assert(isReg() && "Wrong CountValue accessor");  in getReg()
352       assert(isReg() && "Wrong CountValue accessor");  in getSubReg()
362       if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }  in print()
681   if (Op1.isReg()) {  in getLoopTripCount()
701   if (InitialValue->isReg()) {  in getLoopTripCount()
711   if (EndValue->isReg()) {  in getLoopTripCount()
741   if (Start->isReg()) {  in computeCount()
747   if (End->isReg()) {  in computeCount()
754   if (!Start->isReg() && !Start->isImm())  in computeCount()
756   if (!End->isReg() && !End->isImm())  in computeCount()
854   bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm)  in computeCount()
855   bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg)  in computeCount()
893   if (Start->isReg()) {  in computeCount()
1043     if (!MO.isReg() || !MO.isDef())  in isDead()
1062       if (!OPO.isReg() || !OPO.isDef())  in isDead()
1096       if (!MO.isReg() || !MO.isDef())  in removeIfDead()
1211   if (TripCount->isReg()) {  in convertToHardwareLoop()
1247   if (TripCount->isReg()) {  in convertToHardwareLoop()
1340       if (MO.isReg() && MO.isUse()) {  in orderBumpCompare()
1414   if (!InitVal->isReg())  in loopCountMayWrapOrUnderFlow()
1498   if (!MO.isReg())  in checkForImmediate()
1579   assert(MO.isReg());  in setImmediate()
1687   if (!Cond[CSz-1].isReg())  in fixupInductionVariable()
1704     if (MO.isReg()) {  in fixupInductionVariable()
1753           if (MO.isReg() && MO.getReg() == RB.first) {  in fixupInductionVariable()
1761           } else if (MO.isReg()) {  in fixupInductionVariable()
1819         if (MO.isReg() && MO.getReg() == RB.first) {  in fixupInductionVariable()