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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.td88 "Enable VFP2 instructions with "
93 "Enable VFP2 instructions",
96 defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
100 "Enable NEON instructions",
108 defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions",
123 "floating point fml instructions",
129 "Enable divide instructions in Thumb">;
134 "Enable divide instructions in ARM mode">;
138 // True if the subtarget supports DMB / DSB data barrier instructions.
140 "Has data barrier (dmb/dsb) instructions">;
[all …]
H A DARMScheduleM55.td17 // Cortex-M4 are MVE instructions and the ability to dual issue thumb1
18 // instructions.
23 // The EPU pipelines now include both MVE and FP instructions. It has four
28 // forward, if it allows it). This mean that a lot of instructions (including
54 // Cortex-M55 can dual issue two 16-bit T1 instructions providing one is one of
60 // instructions at the point in the pipeline where we do the scheduling. The
63 // instructions will become thumb1 instructions. We are quite optimistic, and
68 // Set IssueWidth to 2 to allow 2 instructions per cycle.
69 // All instructions w
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKY.td23 "Enable FPUv2 single float instructions">;
26 "Enable FPUv2 single float instructions">;
30 "Enable FPUv2 double float instructions">;
33 "Enable FPUv2 double float instructions">;
36 "Enable float divide instructions">;
39 "Enable float divide instructions">;
43 "Enable FPUv3 half word converting instructions">;
46 "Enable FPUv3 half word converting instructions">;
50 "Enable FPUv3 half precision operate instructions">;
53 "Enable FPUv3 half precision operate instructions">;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPC.td59 // Specifies that the selected CPU supports 64-bit instructions, regardless of
62 "Enable 64-bit instructions">;
68 "Enable floating-point instructions">;
80 "Enable classic FPU instructions",
83 "Enable Altivec instructions",
86 "Enable SPE instructions",
89 "Enable Embedded Floating-Point APU 2 instructions",
120 "Enable the fri[mnpz] instructions",
123 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
130 "Enable extended divide instructions">;
[all …]
H A DP10InstrResources.td20 // 2-way crack instructions
40 // 2-way crack instructions
61 // 2-way crack instructions
76 // 2-way crack instructions
249 // 2-way crack instructions
256 // 2-way crack instructions
268 // 2-way crack instructions
295 // 2-way crack instructions
393 // 2-way crack instructions
473 // 2-way crack instructions
[all …]
H A DPPCScheduleP9.td13 // The maximum number of instructions to be issued at the same time.
14 // While a value of 8 is technically correct since 8 instructions can be
15 // fetched from the instruction cache. However, only 6 instructions may be
21 // There are two instructions (lxvl, lxvll) that have a latency of 6 cycles.
23 // of instructions are 4 or 5 cycles.
30 // A dispatch group is 6 instructions.
41 // Do not support SPE (Signal Processing Engine) or prefixed instructions on
43 // instructions introduced after ISA 3.0.
72 // Execution (EXEC) for most other instructions.
73 // Some instructions canno
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagon.td31 "Hexagon ZReg extension instructions">;
33 "true", "Hexagon HVX QFloating point instructions">;
36 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
38 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
41 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
44 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
47 "Hexagon::ArchEnum::V66", "Hexagon HVX instructions",
51 "Hexagon::ArchEnum::V67", "Hexagon HVX instructions",
54 "Hexagon::ArchEnum::V68", "Hexagon HVX instructions",
58 "Hexagon::ArchEnum::V69", "Hexagon HVX instructions",
[all …]
H A DHexagonInstrFormats.td9 // Addressing modes for load/store instructions
64 // instructions to not match without killing the whole decode process. It is
75 // Solo instructions, i.e., those that cannot be in a packet with others.
78 // Packed only with A or X-type instructions.
81 // Restricts slot 1 to ALU-only instructions.
85 // Predicated instructions.
135 // Addressing mode for load/store instructions.
139 // Memory access size for mem access instructions (load/store)
188 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
291 // instructions to not match without killing the whole decode process. It is
[all …]
/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ppccap.pod18 during boot and probe functions that attempt to execute instructions and trap
32 will result in a SIGILL crash. On AIX, all vector instructions can be disabled
34 vector instructions in the OS when it is running on a CPU level that supports the
35 instructions without also disabling them in libcrpto via the OPENSSL_ppccap
52 Meaning: Use AltiVec (aka VMX) instructions. In some but not all cases, this
53 capability gates the use of later ISA vector instructions. The associated probe
56 Effect: Enables use of vector instructions but does not enable extensions added
65 Meaning: Use instructions added in ISA level 2.07. The associated probe
68 Effect: Enables AES, SHA-2 sigma, and other ISA 2.07 instructions for AES, SHA-2,
75 Meaning: Use FPU instructions. The associated probe instruction is fmr (floating
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Features.td57 // Reference Manual. If a SubtargetFeature enables instructions from multiple
72 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
89 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
92 "Enable Armv8.0-A CRC-32 checksum instructions">;
109 "Enable Armv8.1-A Large System Extension (LSE) atomic instructions">;
113 "Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions",
159 "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>;
185 "Enable Armv8.3-A JavaScript FP conversion instructions",
210 "Enable FP16 FML instructions", [FeatureFullFP16]>;
219 "Enable Armv8.4-A Data Independent Timing instructions">;
[all …]
H A DAArch64SchedPredExynos.td16 // Check the shift in arithmetic and logic instructions.
32 // Identify arithmetic instructions without or with limited extension or shift.
60 // Identify logic instructions with limited shift.
76 // Identify more logic instructions with limited shift.
111 // Identify FP instructions.
114 // Identify 128-bit NEON instructions.
117 // Identify instructions that reset a register efficiently.
135 // Identify cheap arithmetic and logic immediate instructions.
H A DAArch64SchedPredicates.td16 // Check the extension type in arithmetic instructions.
28 // Check for shifting in extended arithmetic instructions.
34 // Check for shifting in arithmetic and logic instructions.
52 // Check the shifting type in arithmetic and logic instructions.
93 // Identify arithmetic instructions with extend.
99 // Identify arithmetic immediate instructions.
103 // Identify arithmetic instructions with shift.
107 // Identify arithmetic instructions without shift.
111 // Identify logic immediate instructions.
116 // Identify logic instructions with shift.
[all …]
H A DAArch64SchedExynosM3.td194 // Branch instructions.
198 // Arithmetic and logical integer instructions.
204 // Move instructions.
207 // Divide and multiply instructions.
218 // Miscellaneous instructions.
225 // Load instructions.
231 // Store instructions.
237 // FP data instructions.
244 // FP miscellaneous instructions.
249 // FP load instructions
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td35 "Enabling denormals does not cause f32 instructions to run at f64 rates"
47 "Most fp64 instructions are half rate instead of quarter"
53 "Most fp64 instructions are full rate"
65 "Flat instructions have immediate offset addressing mode"
71 "Have global_* flat memory instructions"
77 "Have scratch_* flat memory instructions"
83 "Have s_scratch_* flat memory instructions"
89 "Use scratch_* flat memory instructions to access scratch"
95 "Have VALU add/sub instructions without carry out"
131 "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
[all …]
H A DSISchedule.td30 // Normal 16 or 32 bit VALU instructions
34 // F16 or F32 transcendental instructions (these are quarter rate)
36 // Other quarter rate VALU instructions
51 // instructions
54 // Half rate 64-bit instructions.
60 // mAI multipass instructions.
68 // Scalar float instructions
71 // F16 or F32 pseudo scalar transcendental instructions
74 // FIXME: Should there be a class for instructions which are VALU
75 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFormats.td27 // When there are multiple instructions that map to the same encoding (in
32 // Normal instructions. Default instantiation of a WebAssemblyInst.
48 // instructions are used for ISel and all MI passes. The stack versions of the
49 // instructions do not have register operands (they implicitly operate on the
50 // stack), and local.gets and local.sets are explicit. The register instructions
51 // are converted to their corresponding stack instructions before lowering to
54 // there is always an equivalent pair of instructions.
64 // For instructions that have no register ops, so both sets are the same.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86.td34 "Enable X87 float instructions">;
40 "Enable conditional move instructions">;
43 "Support CMPXCHG8B instructions">;
52 "Support fxsave/fxrestore instructions">;
55 "Support xsave instructions">;
58 "Support xsaveopt instructions",
62 "Support xsavec instructions",
66 "Support xsaves instructions",
70 "Enable SSE instructions">;
72 "Enable SSE2 instructions",
[all …]
H A DX86InstrInfo.td9 // This file describes the X86 properties of the instructions which are needed
76 // Key Locker instructions
79 // AMX instructions
82 // RAO-INT instructions
85 // System instructions.
H A DX86InstrTDX.td9 // This file describes the instructions that make up the Intel TDX instruction
15 // TDX instructions
17 // 64-bit only instructions
29 // common instructions
H A DX86InstrUtils.td110 // NDD - Helper for new data destination instructions
118 // NF - Helper for NF (no flags update) instructions
120 // PL - Helper for promoted legacy instructions
122 // ZU - Helper for Zero Upper instructions
141 /// InstrSuffix - This is the suffix used on instructions with this type. For
159 /// since the immediate fields of i64 instructions is a 32-bit sign extended
165 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
177 /// only used for instructions that have a sign-extended imm8 field form.
463 // Templates for instructions that use a 16- or 32-bit segmented address as
481 // SI - SSE 1 & 2 scalar instructions
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfbfmin.td1 //===-- RISCVInstrInfoZfbfmin.td - 'Zfbfmin' instructions --*- tablegen -*-===//
9 // This file describes the RISC-V instructions from the standard 'Zfbfmin'
10 // extension, providing scalar conversion instructions for BFloat16.
42 // Pseudo-instructions and codegen patterns
H A DRISCVInstrInfoZvfbf.td1 //===-- RISCVInstrInfoZvfbf.td - 'Zvfbf*' instructions -----*- tablegen -*-===//
9 // This file describes the RISC-V instructions from the standard 'Zvfbfmin'
10 // extension, providing vector conversion instructions for BFloat16.
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td42 // A class for pseudo instructions.
43 // Pseudo instructions are not real AVR instructions. The DAG stores
44 // pseudo instructions which are replaced by real AVR instructions by
49 // the instruction is then replaced by two add instructions - one for each byte.
198 // Special format for the LPM/ELPM instructions
260 // Special encoding for the FMUL family of instructions.
285 // Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|>
411 // Conditional Branching instructions
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMSA.txt7 (semantically equivalent) instructions to be used in place of the requested
14 example, two instructions might be equally valid for some given IR and one is
31 instructions will be selected instead of vshf.[bhwd]. Unlike the ilv*,
32 and pck* instructions, this is matched from MipsISD::VSHF instead of
68 In future, the compiler may choose between these three instructions
71 between the instructions and the vselect node in one place:
/freebsd/contrib/llvm-project/lldb/source/Plugins/TraceExporter/docs/
H A Dhtr.rst9 **Block Metadata:** Metadata associated with each *block*. For processor traces, some metadata examples are the number of instructions in the block or information on what functions are called in the block.
13 **Instruction Layer:** Composed of the load addresses of the instructions in the trace. In an effort to save space,
14 metadata is only stored for instructions that are of interest, not every instruction in the trace. HTR contains a
18 *layer 1* refers to a sequence of instructions in *layer 0* (the instruction layer). Metadata is stored for each block in
22 A pass merges instructions/blocks based on its specific purpose - for example, a pass designed to summarize a processor trace by function calls would merge all the blocks of a function into a single block representing the entire function.
31 A *pass* is applied to a *layer* to extract useful information (summarization) and compress the trace representation into a new *layer*. The idea is to have a series of passes where each pass specializes in extracting certain information about the trace. Some examples of potential passes include: identifying functions, identifying loops, or a more general purpose such as identifying long sequences of instructions that are repeated (i.e. Basic Super Block). Below you will find a description of each pass currently implemented in lldb.

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