1=pod 2 3=head1 NAME 4 5OPENSSL_ppccap - the PowerPC processor capabilities vector 6 7=head1 SYNOPSIS 8 9 env OPENSSL_ppccap=... <application> 10 11=head1 DESCRIPTION 12 13libcrypto supports PowerPC instruction set extensions. These extensions are 14represented by bits in the PowerPC capabilities vector. When libcrypto 15initializes, it stores the results returned by PowerPC CPU capabilities detection 16logic in the PowerPC capabilities vector. The CPU capabilities detection methods 17are OS-dependent and use a combination of information gathered by the kernel 18during boot and probe functions that attempt to execute instructions and trap 19illegal instruction signals with a signal handler. 20 21To override the set of extensions available to an application, you can set the 22B<OPENSSL_ppccap> environment variable before you start the application. The 23environment variable is assigned a numerical value that denotes the bits in 24the PowerPC capabilities vector. The ppc_arch.h header file states that, "Flags' 25usage can appear ambiguous, because they are set rather to reflect OpenSSL 26performance preferences than actual processor capabilities." 27 28Multiple extensions are enabled by logically OR-ing the values that represent the 29desired extensions. 30 31B<Notes>: Enabling an extension on a CPU that does not support the extension 32will result in a SIGILL crash. On AIX, all vector instructions can be disabled 33with the schedo -ro allow_vmx=0 command. DO NOT USE THIS COMMAND to disable 34vector instructions in the OS when it is running on a CPU level that supports the 35instructions without also disabling them in libcrpto via the OPENSSL_ppccap 36environment variable or the application will crash with a SIGILL. 37 38Currently, the following extensions are defined: 39 40=over 4 41 42=item 0x01 43 44Name: B<PPC_FPU64> 45 46This flag is obsolete. 47 48=item 0x02 49 50Name: B<PPC_ALTIVEC> 51 52Meaning: Use AltiVec (aka VMX) instructions. In some but not all cases, this 53capability gates the use of later ISA vector instructions. The associated probe 54instruction is vor (vector logical or). 55 56Effect: Enables use of vector instructions but does not enable extensions added 57at specific ISA levels. However, disabling this capability disables a subset of 58vector extensions added at specific ISA levels even if they are otherwise 59enabled. 60 61=item 0x04 62 63Name: B<PPC_CRYPTO207> 64 65Meaning: Use instructions added in ISA level 2.07. The associated probe 66instruction instruction is vcipher (vector AES cipher round). 67 68Effect: Enables AES, SHA-2 sigma, and other ISA 2.07 instructions for AES, SHA-2, 69GHASH, and Poly1305. 70 71=item 0x08 72 73Name: B<PPC_FPU> 74 75Meaning: Use FPU instructions. The associated probe instruction is fmr (floating 76move register). 77 78Effect: Enables Poly1305 FPU implementation. The PPC_CRYPTO207 capability 79overrides this effect. 80 81=item 0x10 82 83Name: B<PPC_MADD300> 84 85Meaning: Use instructions added in ISA level 3.00. The associated probe 86instruction is maddhdu (multiply-add high doubleword unsigned). 87 88Effect: Enables use of the polynomial multiply and other ISA 3.00 instructions 89for AES-GCM, P-384, and P-521. 90 91=item 0x20 92 93Name: B<PPC_MFTB> 94 95Meaning: Use the mftb (move from time base) instruction. The associated probe 96instruction is mftb. 97 98Effect: Enables use of the mftb instruction to sample the lower 32 bits of the 99CPU time base register in order to acquire entropy. Considered obsolete. The 100PPC_MFSPR268 capability overrides this capability. 101 102=item 0x40 103 104Name: B<PPC_MFSPR268> 105 106Meaning: Use the mfspr (move from special purpose register) instruction to 107read SPR 268. The associated probe instruction is mfspr 268. 108 109Effect: Enables use of the mfspr instruction to sample the lower 32 bits of the 110CPU time base register from SPR 268, the TBL (time base lower) register, in order 111to acquire entropy. 112 113=item 0x80 114 115Name: B<PPC_BRD31> 116 117Meaning: Use instructions added in ISA level 3.1. The associated probe instruction 118is brd (byte-reverse doubleword). 119 120Effect: Enables use of ISA 3.1 instructions in ChaCha20. 121 122=back 123 124=head1 RETURN VALUES 125 126Not available. 127 128=head1 EXAMPLES 129 130Check currently detected capabilities: 131 132 $ openssl info -cpusettings 133 OPENSSL_ppccap=0x2E 134 135The detected capabilities in the above example indicate that PPC_MFTB, PPC_FPU, 136PPC_CRYPTO207, PPC_MFSPR268, and PPC_ALTIVEC are enabled. 137 138Disable all instruction set extensions: 139 140 OPENSSL_ppccap=0x00 141 142Enable base AltiVec extensions: 143 144 OPENSSL_ppccap=0x02 145 146=head1 COPYRIGHT 147 148Copyright 2025 The OpenSSL Project Authors. All Rights Reserved. 149 150Licensed under the Apache License 2.0 (the "License"). You may not use 151this file except in compliance with the License. You can obtain a copy 152in the file LICENSE in the source distribution or at 153L<https://www.openssl.org/source/license.html>. 154 155=cut 156