1//===--- P10InstrResources.td - P10 Scheduling Definitions -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// Automatically generated file, do not edit! 9// 10// This file defines instruction data for SchedModel of the POWER10 processor. 11// 12//===----------------------------------------------------------------------===// 13// 22 Cycles Binary Floating Point operations, 2 input operands 14def : InstRW<[P10W_BF_22C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 15 (instrs 16 FDIVS, 17 XSDIVSP 18)>; 19 20// 2-way crack instructions 21// 22 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 22def : InstRW<[P10W_BF_22C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 23 (instrs 24 FDIVS_rec 25)>; 26 27// 24 Cycles Binary Floating Point operations, 2 input operands 28def : InstRW<[P10W_BF_24C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 29 (instrs 30 XVDIVSP 31)>; 32 33// 26 Cycles Binary Floating Point operations, 1 input operands 34def : InstRW<[P10W_BF_26C, P10W_DISP_ANY, P10BF_Read], 35 (instrs 36 FSQRTS, 37 XSSQRTSP 38)>; 39 40// 2-way crack instructions 41// 26 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 42def : InstRW<[P10W_BF_26C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 43 (instrs 44 FSQRTS_rec 45)>; 46 47// 27 Cycles Binary Floating Point operations, 1 input operands 48def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read], 49 (instrs 50 XVSQRTSP 51)>; 52 53// 27 Cycles Binary Floating Point operations, 2 input operands 54def : InstRW<[P10W_BF_27C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 55 (instrs 56 FDIV, 57 XSDIVDP, 58 XVDIVDP 59)>; 60 61// 2-way crack instructions 62// 27 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 63def : InstRW<[P10W_BF_27C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 64 (instrs 65 FDIV_rec 66)>; 67 68// 36 Cycles Binary Floating Point operations, 1 input operands 69def : InstRW<[P10W_BF_36C, P10W_DISP_ANY, P10BF_Read], 70 (instrs 71 FSQRT, 72 XSSQRTDP, 73 XVSQRTDP 74)>; 75 76// 2-way crack instructions 77// 36 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 78def : InstRW<[P10W_BF_36C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 79 (instrs 80 FSQRT_rec 81)>; 82 83// 7 Cycles Binary Floating Point operations, 1 input operands 84def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 85 (instrs 86 FCFID, 87 FCFIDS, 88 FCFIDU, 89 FCFIDUS, 90 FCTID, 91 FCTIDU, 92 FCTIDUZ, 93 FCTIDZ, 94 FCTIW, 95 FCTIWU, 96 FCTIWUZ, 97 FCTIWZ, 98 FRE, 99 FRES, 100 FRIMD, FRIMS, 101 FRIND, FRINS, 102 FRIPD, FRIPS, 103 FRIZD, FRIZS, 104 FRSP, 105 FRSQRTE, 106 FRSQRTES, 107 VCFSX, VCFSX_0, 108 VCFUX, VCFUX_0, 109 VCTSXS, VCTSXS_0, 110 VCTUXS, VCTUXS_0, 111 VLOGEFP, 112 VREFP, 113 VRFIM, 114 VRFIN, 115 VRFIP, 116 VRFIZ, 117 VRSQRTEFP, 118 XSCVDPHP, 119 XSCVDPSP, 120 XSCVDPSPN, 121 XSCVDPSXDS, XSCVDPSXDSs, 122 XSCVDPSXWS, XSCVDPSXWSs, 123 XSCVDPUXDS, XSCVDPUXDSs, 124 XSCVDPUXWS, XSCVDPUXWSs, 125 XSCVSPDP, 126 XSCVSXDDP, 127 XSCVSXDSP, 128 XSCVUXDDP, 129 XSCVUXDSP, 130 XSRDPI, 131 XSRDPIC, 132 XSRDPIM, 133 XSRDPIP, 134 XSRDPIZ, 135 XSREDP, 136 XSRESP, 137 XSRSP, 138 XSRSQRTEDP, 139 XSRSQRTESP, 140 XVCVDPSP, 141 XVCVDPSXDS, 142 XVCVDPSXWS, 143 XVCVDPUXDS, 144 XVCVDPUXWS, 145 XVCVSPBF16, 146 XVCVSPDP, 147 XVCVSPHP, 148 XVCVSPSXDS, 149 XVCVSPSXWS, 150 XVCVSPUXDS, 151 XVCVSPUXWS, 152 XVCVSXDDP, 153 XVCVSXDSP, 154 XVCVSXWDP, 155 XVCVSXWSP, 156 XVCVUXDDP, 157 XVCVUXDSP, 158 XVCVUXWDP, 159 XVCVUXWSP, 160 XVRDPI, 161 XVRDPIC, 162 XVRDPIM, 163 XVRDPIP, 164 XVRDPIZ, 165 XVREDP, 166 XVRESP, 167 XVRSPI, 168 XVRSPIC, 169 XVRSPIM, 170 XVRSPIP, 171 XVRSPIZ, 172 XVRSQRTEDP, 173 XVRSQRTESP 174)>; 175 176// 7 Cycles Binary Floating Point operations, 2 input operands 177def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read], 178 (instrs 179 FADD, 180 FADDS, 181 FMUL, 182 FMULS, 183 FSUB, 184 FSUBS, 185 VADDFP, 186 VSUBFP, 187 XSADDDP, 188 XSADDSP, 189 XSMULDP, 190 XSMULSP, 191 XSSUBDP, 192 XSSUBSP, 193 XVADDDP, 194 XVADDSP, 195 XVMULDP, 196 XVMULSP, 197 XVSUBDP, 198 XVSUBSP 199)>; 200 201// 7 Cycles Binary Floating Point operations, 3 input operands 202def : InstRW<[P10W_BF_7C, P10W_DISP_ANY, P10BF_Read, P10BF_Read, P10BF_Read], 203 (instrs 204 FMADD, 205 FMADDS, 206 FMSUB, 207 FMSUBS, 208 FNMADD, 209 FNMADDS, 210 FNMSUB, 211 FNMSUBS, 212 FSELD, FSELS, 213 VMADDFP, 214 VNMSUBFP, 215 XSMADDADP, 216 XSMADDASP, 217 XSMADDMDP, 218 XSMADDMSP, 219 XSMSUBADP, 220 XSMSUBASP, 221 XSMSUBMDP, 222 XSMSUBMSP, 223 XSNMADDADP, 224 XSNMADDASP, 225 XSNMADDMDP, 226 XSNMADDMSP, 227 XSNMSUBADP, 228 XSNMSUBASP, 229 XSNMSUBMDP, 230 XSNMSUBMSP, 231 XVMADDADP, 232 XVMADDASP, 233 XVMADDMDP, 234 XVMADDMSP, 235 XVMSUBADP, 236 XVMSUBASP, 237 XVMSUBMDP, 238 XVMSUBMSP, 239 XVNMADDADP, 240 XVNMADDASP, 241 XVNMADDMDP, 242 XVNMADDMSP, 243 XVNMSUBADP, 244 XVNMSUBASP, 245 XVNMSUBMDP, 246 XVNMSUBMSP 247)>; 248 249// 2-way crack instructions 250// 7 Cycles Binary Floating Point operations, and 7 Cycles Binary Floating Point operations, 1 input operands 251def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_BF_7C, P10W_DISP_ANY, P10BF_Read], 252 (instrs 253 VEXPTEFP 254)>; 255 256// 2-way crack instructions 257// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 2 input operands 258def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 259 (instrs 260 FADD_rec, 261 FADDS_rec, 262 FMUL_rec, 263 FMULS_rec, 264 FSUB_rec, 265 FSUBS_rec 266)>; 267 268// 2-way crack instructions 269// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 1 input operands 270def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 271 (instrs 272 FCFID_rec, 273 FCFIDS_rec, 274 FCFIDU_rec, 275 FCFIDUS_rec, 276 FCTID_rec, 277 FCTIDU_rec, 278 FCTIDUZ_rec, 279 FCTIDZ_rec, 280 FCTIW_rec, 281 FCTIWU_rec, 282 FCTIWUZ_rec, 283 FCTIWZ_rec, 284 FRE_rec, 285 FRES_rec, 286 FRIMD_rec, FRIMS_rec, 287 FRIND_rec, FRINS_rec, 288 FRIPD_rec, FRIPS_rec, 289 FRIZD_rec, FRIZS_rec, 290 FRSP_rec, 291 FRSQRTE_rec, 292 FRSQRTES_rec 293)>; 294 295// 2-way crack instructions 296// 7 Cycles Binary Floating Point operations, and 3 Cycles ALU operations, 3 input operands 297def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 298 (instrs 299 FMADD_rec, 300 FMADDS_rec, 301 FMSUB_rec, 302 FMSUBS_rec, 303 FNMADD_rec, 304 FNMADDS_rec, 305 FNMSUB_rec, 306 FNMSUBS_rec, 307 FSELD_rec, FSELS_rec 308)>; 309 310// 2 Cycles Branch operations, 1 input operands 311def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read], 312 (instrs 313 B, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, CTRL_DEP, TAILB, TAILB8, 314 BA, TAILBA, TAILBA8, 315 BCCTR, BCCTR8, BCCTR8n, BCCTRn, gBCCTR, 316 BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, gBCCTRL, 317 BCLR, BCLRn, BDNZLR, BDNZLR8, BDNZLRm, BDNZLRp, BDZLR, BDZLR8, BDZLRm, BDZLRp, gBCLR, 318 BCLRL, BCLRLn, BDNZLRL, BDNZLRLm, BDNZLRLp, BDZLRL, BDZLRLm, BDZLRLp, gBCLRL, 319 BL, BL8, BL8_NOP, BL8_NOP_RM, BL8_NOP_TLS, BL8_NOTOC, BL8_NOTOC_RM, BL8_NOTOC_TLS, BL8_RM, BL8_TLS, BL8_TLS_, BLR, BLR8, BLRL, BL_NOP, BL_NOP_RM, BL_RM, BL_TLS, 320 BLA, BLA8, BLA8_NOP, BLA8_NOP_RM, BLA8_RM, BLA_RM 321)>; 322 323// 2 Cycles Branch operations, 2 input operands 324def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read, P10BR_Read], 325 (instrs 326 BC, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM, BCTRL_RM, BCn, BDNZ, BDNZ8, BDNZm, BDNZp, BDZ, BDZ8, BDZm, BDZp, TAILBCTR, TAILBCTR8, gBC, gBCat, 327 BDNZA, BDNZAm, BDNZAp, BDZA, BDZAm, BDZAp, gBCA, gBCAat, 328 BCL, BCLalways, BCLn, BDNZL, BDNZLm, BDNZLp, BDZL, BDZLm, BDZLp, gBCL, gBCLat, 329 BDNZLA, BDNZLAm, BDNZLAp, BDZLA, BDZLAm, BDZLAp, gBCLA, gBCLAat 330)>; 331 332// 7 Cycles Crypto operations, 1 input operands 333def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read], 334 (instrs 335 VGNB, 336 VSBOX 337)>; 338 339// 7 Cycles Crypto operations, 2 input operands 340def : InstRW<[P10W_CY_7C, P10W_DISP_ANY, P10CY_Read, P10CY_Read], 341 (instrs 342 CFUGED, 343 CNTLZDM, 344 CNTTZDM, 345 PDEPD, 346 PEXTD, 347 VCFUGED, 348 VCIPHER, 349 VCIPHERLAST, 350 VCLZDM, 351 VCTZDM, 352 VNCIPHER, 353 VNCIPHERLAST, 354 VPDEPD, 355 VPEXTD, 356 VPMSUMB, 357 VPMSUMD, 358 VPMSUMH, 359 VPMSUMW 360)>; 361 362// 13 Cycles Decimal Floating Point operations, 1 input operands 363def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read], 364 (instrs 365 XSCVDPQP, 366 XSCVQPDP, 367 XSCVQPDPO, 368 XSCVQPSDZ, 369 XSCVQPSQZ, 370 XSCVQPSWZ, 371 XSCVQPUDZ, 372 XSCVQPUQZ, 373 XSCVQPUWZ, 374 XSCVSDQP, 375 XSCVSQQP, 376 XSCVUDQP, 377 XSCVUQQP, 378 XSRQPI, 379 XSRQPIX, 380 XSRQPXP 381)>; 382 383// 13 Cycles Decimal Floating Point operations, 2 input operands 384def : InstRW<[P10W_DF_13C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 385 (instrs 386 BCDSR_rec, 387 XSADDQP, 388 XSADDQPO, 389 XSSUBQP, 390 XSSUBQPO 391)>; 392 393// 2-way crack instructions 394// 13 Cycles Decimal Floating Point operations, and 3 Cycles Store operations, 1 input operands 395def : InstRW<[P10W_DF_13C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY], 396 (instrs 397 HASHST, HASHST8, 398 HASHSTP, HASHSTP8 399)>; 400 401// 24 Cycles Decimal Floating Point operations, 1 input operands 402def : InstRW<[P10W_DF_24C, P10W_DISP_ANY, P10DF_Read], 403 (instrs 404 BCDCTSQ_rec 405)>; 406 407// 25 Cycles Decimal Floating Point operations, 2 input operands 408def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 409 (instrs 410 XSMULQP, 411 XSMULQPO 412)>; 413 414// 25 Cycles Decimal Floating Point operations, 3 input operands 415def : InstRW<[P10W_DF_25C, P10W_DISP_ANY, P10DF_Read, P10DF_Read, P10DF_Read], 416 (instrs 417 XSMADDQP, 418 XSMADDQPO, 419 XSMSUBQP, 420 XSMSUBQPO, 421 XSNMADDQP, 422 XSNMADDQPO, 423 XSNMSUBQP, 424 XSNMSUBQPO 425)>; 426 427// 38 Cycles Decimal Floating Point operations, 1 input operands 428def : InstRW<[P10W_DF_38C, P10W_DISP_ANY, P10DF_Read], 429 (instrs 430 BCDCFSQ_rec 431)>; 432 433// 59 Cycles Decimal Floating Point operations, 2 input operands 434def : InstRW<[P10W_DF_59C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 435 (instrs 436 XSDIVQP, 437 XSDIVQPO 438)>; 439 440// 61 Cycles Decimal Floating Point operations, 2 input operands 441def : InstRW<[P10W_DF_61C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 442 (instrs 443 VDIVESQ, 444 VDIVEUQ, 445 VDIVSQ, 446 VDIVUQ 447)>; 448 449// 68 Cycles Decimal Floating Point operations, 2 input operands 450def : InstRW<[P10W_DF_68C, P10W_DISP_ANY, P10DF_Read, P10DF_Read], 451 (instrs 452 VMODSQ, 453 VMODUQ 454)>; 455 456// 77 Cycles Decimal Floating Point operations, 1 input operands 457def : InstRW<[P10W_DF_77C, P10W_DISP_ANY, P10DF_Read], 458 (instrs 459 XSSQRTQP, 460 XSSQRTQPO 461)>; 462 463// 20 Cycles Scalar Fixed-Point Divide operations, 2 input operands 464def : InstRW<[P10W_DV_20C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 465 (instrs 466 DIVW, 467 DIVWO, 468 DIVWU, 469 DIVWUO, 470 MODSW 471)>; 472 473// 2-way crack instructions 474// 20 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 475def : InstRW<[P10W_DV_20C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 476 (instrs 477 DIVW_rec, 478 DIVWO_rec, 479 DIVWU_rec, 480 DIVWUO_rec 481)>; 482 483// 25 Cycles Scalar Fixed-Point Divide operations, 2 input operands 484def : InstRW<[P10W_DV_25C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 485 (instrs 486 DIVD, 487 DIVDO, 488 DIVDU, 489 DIVDUO, 490 DIVWE, 491 DIVWEO, 492 DIVWEU, 493 DIVWEUO 494)>; 495 496// 2-way crack instructions 497// 25 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 498def : InstRW<[P10W_DV_25C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 499 (instrs 500 DIVD_rec, 501 DIVDO_rec, 502 DIVDU_rec, 503 DIVDUO_rec, 504 DIVWE_rec, 505 DIVWEO_rec, 506 DIVWEU_rec, 507 DIVWEUO_rec 508)>; 509 510// 27 Cycles Scalar Fixed-Point Divide operations, 2 input operands 511def : InstRW<[P10W_DV_27C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 512 (instrs 513 MODSD, 514 MODUD, 515 MODUW 516)>; 517 518// 41 Cycles Scalar Fixed-Point Divide operations, 2 input operands 519def : InstRW<[P10W_DV_41C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 520 (instrs 521 DIVDE, 522 DIVDEO, 523 DIVDEU, 524 DIVDEUO 525)>; 526 527// 2-way crack instructions 528// 41 Cycles Scalar Fixed-Point Divide operations, and 3 Cycles ALU operations, 2 input operands 529def : InstRW<[P10W_DV_41C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 530 (instrs 531 DIVDE_rec, 532 DIVDEO_rec, 533 DIVDEU_rec, 534 DIVDEUO_rec 535)>; 536 537// 43 Cycles Scalar Fixed-Point Divide operations, 2 input operands 538def : InstRW<[P10W_DV_43C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 539 (instrs 540 VDIVSD, 541 VDIVUD 542)>; 543 544// 47 Cycles Scalar Fixed-Point Divide operations, 2 input operands 545def : InstRW<[P10W_DV_47C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 546 (instrs 547 VMODSD, 548 VMODUD 549)>; 550 551// 54 Cycles Scalar Fixed-Point Divide operations, 2 input operands 552def : InstRW<[P10W_DV_54C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 553 (instrs 554 VDIVSW, 555 VDIVUW 556)>; 557 558// 60 Cycles Scalar Fixed-Point Divide operations, 2 input operands 559def : InstRW<[P10W_DV_60C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 560 (instrs 561 VMODSW, 562 VMODUW 563)>; 564 565// 75 Cycles Scalar Fixed-Point Divide operations, 2 input operands 566def : InstRW<[P10W_DV_75C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 567 (instrs 568 VDIVESD, 569 VDIVEUD 570)>; 571 572// 83 Cycles Scalar Fixed-Point Divide operations, 2 input operands 573def : InstRW<[P10W_DV_83C, P10W_DISP_ANY, P10DV_Read, P10DV_Read], 574 (instrs 575 VDIVESW, 576 VDIVEUW 577)>; 578 579// 5 Cycles Fixed-Point and BCD operations, 1 input operands 580def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read], 581 (instrs 582 BCDCFN_rec, 583 BCDCFZ_rec, 584 BCDCTN_rec, 585 BCDCTZ_rec, 586 BCDSETSGN_rec, 587 VMUL10CUQ, 588 VMUL10UQ, 589 XSTSTDCQP, 590 XSXSIGQP, 591 XXGENPCVBM 592)>; 593 594// 5 Cycles Fixed-Point and BCD operations, 2 input operands 595def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read], 596 (instrs 597 BCDADD_rec, 598 BCDCPSGN_rec, 599 BCDS_rec, 600 BCDSUB_rec, 601 BCDTRUNC_rec, 602 BCDUS_rec, 603 BCDUTRUNC_rec, 604 VADDCUQ, 605 VADDUQM, 606 VMUL10ECUQ, 607 VMUL10EUQ, 608 VSUBCUQ, 609 VSUBUQM, 610 XSCMPEQQP, 611 XSCMPEXPQP, 612 XSCMPGEQP, 613 XSCMPGTQP, 614 XSCMPOQP, 615 XSCMPUQP, 616 XSMAXCQP, 617 XSMINCQP 618)>; 619 620// 5 Cycles Fixed-Point and BCD operations, 3 input operands 621def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read, P10DX_Read], 622 (instrs 623 VADDECUQ, 624 VADDEUQM, 625 VSUBECUQ, 626 VSUBEUQM 627)>; 628 629// 4 Cycles ALU2 operations, 0 input operands 630def : InstRW<[P10W_F2_4C, P10W_DISP_ANY], 631 (instrs 632 MTVSRBMI 633)>; 634 635// 4 Cycles ALU2 operations, 1 input operands 636def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read], 637 (instrs 638 CBCDTD, CBCDTD8, 639 CDTBCD, CDTBCD8, 640 CNTLZD, 641 CNTLZD_rec, 642 CNTLZW, CNTLZW8, 643 CNTLZW8_rec, CNTLZW_rec, 644 CNTTZD, 645 CNTTZD_rec, 646 CNTTZW, CNTTZW8, 647 CNTTZW8_rec, CNTTZW_rec, 648 EXTSWSLI_32_64_rec, EXTSWSLI_rec, 649 FTSQRT, 650 MTVSRBM, 651 MTVSRDM, 652 MTVSRHM, 653 MTVSRQM, 654 MTVSRWM, 655 POPCNTB, POPCNTB8, 656 POPCNTD, 657 POPCNTW, 658 RLDIC_rec, 659 RLDICL_32_rec, RLDICL_rec, 660 RLDICR_rec, 661 RLWINM8_rec, RLWINM_rec, 662 VCLZB, 663 VCLZD, 664 VCLZH, 665 VCLZW, 666 VCNTMBB, 667 VCNTMBD, 668 VCNTMBH, 669 VCNTMBW, 670 VCTZB, 671 VCTZD, 672 VCTZH, 673 VCTZW, 674 VEXPANDBM, 675 VEXPANDDM, 676 VEXPANDHM, 677 VEXPANDQM, 678 VEXPANDWM, 679 VEXTRACTBM, 680 VEXTRACTDM, 681 VEXTRACTHM, 682 VEXTRACTQM, 683 VEXTRACTWM, 684 VPOPCNTB, 685 VPOPCNTD, 686 VPOPCNTH, 687 VPOPCNTW, 688 VPRTYBD, 689 VPRTYBW, 690 VSHASIGMAD, 691 VSHASIGMAW, 692 XSCVHPDP, 693 XSCVSPDPN, 694 XSTSQRTDP, 695 XSTSTDCDP, 696 XSTSTDCSP, 697 XVCVHPSP, 698 XVTLSBB, 699 XVTSQRTDP, 700 XVTSQRTSP, 701 XVTSTDCDP, 702 XVTSTDCSP 703)>; 704 705// 4 Cycles ALU2 operations, 2 input operands 706def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 707 (instrs 708 CMPEQB, 709 CMPRB, CMPRB8, 710 FCMPOD, FCMPOS, 711 FCMPUD, FCMPUS, 712 FTDIV, 713 RLDCL_rec, 714 RLDCR_rec, 715 RLDIMI_rec, 716 RLWIMI8_rec, RLWIMI_rec, 717 RLWNM8_rec, RLWNM_rec, 718 SLD_rec, 719 SLW8_rec, SLW_rec, 720 SRD_rec, 721 SRW8_rec, SRW_rec, 722 TDI, 723 TWI, 724 VABSDUB, 725 VABSDUH, 726 VABSDUW, 727 VADDCUW, 728 VADDSBS, 729 VADDSHS, 730 VADDSWS, 731 VADDUBS, 732 VADDUHS, 733 VADDUWS, 734 VAVGSB, 735 VAVGSH, 736 VAVGSW, 737 VAVGUB, 738 VAVGUH, 739 VAVGUW, 740 VCMPBFP, 741 VCMPBFP_rec, 742 VCMPEQFP, 743 VCMPEQFP_rec, 744 VCMPEQUB_rec, 745 VCMPEQUD_rec, 746 VCMPEQUH_rec, 747 VCMPEQUQ, 748 VCMPEQUQ_rec, 749 VCMPEQUW_rec, 750 VCMPGEFP, 751 VCMPGEFP_rec, 752 VCMPGTFP, 753 VCMPGTFP_rec, 754 VCMPGTSB_rec, 755 VCMPGTSD_rec, 756 VCMPGTSH_rec, 757 VCMPGTSQ, 758 VCMPGTSQ_rec, 759 VCMPGTSW_rec, 760 VCMPGTUB_rec, 761 VCMPGTUD_rec, 762 VCMPGTUH_rec, 763 VCMPGTUQ, 764 VCMPGTUQ_rec, 765 VCMPGTUW_rec, 766 VCMPNEB_rec, 767 VCMPNEH_rec, 768 VCMPNEW_rec, 769 VCMPNEZB_rec, 770 VCMPNEZH_rec, 771 VCMPNEZW_rec, 772 VCMPSQ, 773 VCMPUQ, 774 VMAXFP, 775 VMINFP, 776 VSUBCUW, 777 VSUBSBS, 778 VSUBSHS, 779 VSUBSWS, 780 VSUBUBS, 781 VSUBUHS, 782 VSUBUWS, 783 XSCMPEQDP, 784 XSCMPEXPDP, 785 XSCMPGEDP, 786 XSCMPGTDP, 787 XSCMPODP, 788 XSCMPUDP, 789 XSMAXCDP, 790 XSMAXDP, 791 XSMAXJDP, 792 XSMINCDP, 793 XSMINDP, 794 XSMINJDP, 795 XSTDIVDP, 796 XVCMPEQDP, 797 XVCMPEQDP_rec, 798 XVCMPEQSP, 799 XVCMPEQSP_rec, 800 XVCMPGEDP, 801 XVCMPGEDP_rec, 802 XVCMPGESP, 803 XVCMPGESP_rec, 804 XVCMPGTDP, 805 XVCMPGTDP_rec, 806 XVCMPGTSP, 807 XVCMPGTSP_rec, 808 XVMAXDP, 809 XVMAXSP, 810 XVMINDP, 811 XVMINSP, 812 XVTDIVDP, 813 XVTDIVSP 814)>; 815 816// 4 Cycles ALU2 operations, 3 input operands 817def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read], 818 (instrs 819 TD, 820 TRAP, TW 821)>; 822 823// Single crack instructions 824// 4 Cycles ALU2 operations, 1 input operands 825def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read], 826 (instrs 827 SRADI_rec, 828 SRAWI_rec 829)>; 830 831// Single crack instructions 832// 4 Cycles ALU2 operations, 2 input operands 833def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read], 834 (instrs 835 SRAD_rec, 836 SRAW_rec 837)>; 838 839// 2-way crack instructions 840// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 2 input operands 841def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 842 (instrs 843 VRLQ, 844 VRLQNM, 845 VSLQ, 846 VSRAQ, 847 VSRQ 848)>; 849 850// 2-way crack instructions 851// 4 Cycles ALU2 operations, and 4 Cycles Permute operations, 3 input operands 852def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 853 (instrs 854 VRLQMI 855)>; 856 857// 2-way crack instructions 858// 4 Cycles ALU2 operations, and 4 Cycles ALU2 operations, 0 input operands 859def : InstRW<[P10W_F2_4C, P10W_DISP_PAIR, P10W_F2_4C], 860 (instrs 861 MFCR, MFCR8 862)>; 863 864// 2 Cycles ALU operations, 1 input operands 865def : InstRW<[P10W_FX_2C, P10W_DISP_ANY, P10FX_Read], 866 (instrs 867 MTCTR, MTCTR8, MTCTR8loop, MTCTRloop, 868 MTLR, MTLR8 869)>; 870 871// 3 Cycles ALU operations, 0 input operands 872def : InstRW<[P10W_FX_3C, P10W_DISP_ANY], 873 (instrs 874 DSS, DSSALL, 875 MCRXRX, 876 MFCTR, MFCTR8, 877 MFLR, MFLR8, 878 WAIT, WAITP10 879)>; 880 881// 3 Cycles ALU operations, 1 input operands 882def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 883 (instrs 884 ADDI, ADDI8, ADDIdtprelL32, ADDItlsldLADDR32, ADDItocL, ADDItocL8, LI, LI8, 885 ADDIC, ADDIC8, 886 ADDIS, ADDIS8, ADDISdtprelHA32, ADDIStocHA, ADDIStocHA8, LIS, LIS8, 887 ADDME, ADDME8, 888 ADDME8O, ADDMEO, 889 ADDZE, ADDZE8, 890 ADDZE8O, ADDZEO, 891 ANDI8_rec, ANDI_rec, 892 ANDIS8_rec, ANDIS_rec, 893 CMPDI, CMPWI, 894 CMPLDI, CMPLWI, 895 EXTSB, EXTSB8, EXTSB8_32_64, 896 EXTSB8_rec, EXTSB_rec, 897 EXTSH, EXTSH8, EXTSH8_32_64, 898 EXTSH8_rec, EXTSH_rec, 899 EXTSW, EXTSW_32, EXTSW_32_64, 900 EXTSW_32_64_rec, EXTSW_rec, 901 EXTSWSLI, EXTSWSLI_32_64, 902 FABSD, FABSS, 903 FMR, 904 FNABSD, FNABSS, 905 FNEGD, FNEGS, 906 MCRF, 907 MFOCRF, MFOCRF8, 908 MFVRD, MFVSRD, 909 MFVRWZ, MFVSRWZ, 910 MTOCRF, MTOCRF8, 911 MTVRD, MTVSRD, 912 MTVRWA, MTVSRWA, 913 MTVRWZ, MTVSRWZ, 914 NEG, NEG8, 915 NEG8_rec, NEG_rec, 916 NEG8O, NEGO, 917 NOP, NOP_GT_PWR6, NOP_GT_PWR7, ORI, ORI8, 918 ORIS, ORIS8, 919 RLDIC, 920 RLDICL, RLDICL_32, RLDICL_32_64, 921 RLDICR, RLDICR_32, 922 RLWINM, RLWINM8, 923 SETB, SETB8, 924 SETBC, SETBC8, 925 SETBCR, SETBCR8, 926 SETNBC, SETNBC8, 927 SETNBCR, SETNBCR8, 928 SRADI, SRADI_32, 929 SRAWI, 930 SUBFIC, SUBFIC8, 931 SUBFME, SUBFME8, 932 SUBFME8O, SUBFMEO, 933 SUBFZE, SUBFZE8, 934 SUBFZE8O, SUBFZEO, 935 VEXTSB2D, VEXTSB2Ds, 936 VEXTSB2W, VEXTSB2Ws, 937 VEXTSD2Q, 938 VEXTSH2D, VEXTSH2Ds, 939 VEXTSH2W, VEXTSH2Ws, 940 VEXTSW2D, VEXTSW2Ds, 941 VNEGD, 942 VNEGW, 943 XORI, XORI8, 944 XORIS, XORIS8, 945 XSABSDP, 946 XSABSQP, 947 XSNABSDP, XSNABSDPs, 948 XSNABSQP, 949 XSNEGDP, 950 XSNEGQP, 951 XSXEXPDP, 952 XSXEXPQP, 953 XSXSIGDP, 954 XVABSDP, 955 XVABSSP, 956 XVNABSDP, 957 XVNABSSP, 958 XVNEGDP, 959 XVNEGSP, 960 XVXEXPDP, 961 XVXEXPSP, 962 XVXSIGDP, 963 XVXSIGSP 964)>; 965 966// 3 Cycles ALU operations, 2 input operands 967def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 968 (instrs 969 ADD4, ADD4TLS, ADD8, ADD8TLS, ADD8TLS_, 970 ADD4_rec, ADD8_rec, 971 ADDE, ADDE8, 972 ADDE8O, ADDEO, 973 ADDEX, ADDEX8, 974 ADD4O, ADD8O, 975 AND, AND8, 976 AND8_rec, AND_rec, 977 ANDC, ANDC8, 978 ANDC8_rec, ANDC_rec, 979 CMPD, CMPW, 980 CMPB, CMPB8, 981 CMPLD, CMPLW, 982 CRAND, 983 CRANDC, 984 CR6SET, CREQV, CRSET, 985 CRNAND, 986 CRNOR, 987 CROR, 988 CRORC, 989 CR6UNSET, CRUNSET, CRXOR, 990 DST, DST64, DSTT, DSTT64, 991 DSTST, DSTST64, DSTSTT, DSTSTT64, 992 EQV, EQV8, 993 EQV8_rec, EQV_rec, 994 FCPSGND, FCPSGNS, 995 NAND, NAND8, 996 NAND8_rec, NAND_rec, 997 NOR, NOR8, 998 NOR8_rec, NOR_rec, 999 COPY, OR, OR8, 1000 OR8_rec, OR_rec, 1001 ORC, ORC8, 1002 ORC8_rec, ORC_rec, 1003 RLDCL, 1004 RLDCR, 1005 RLDIMI, 1006 RLWIMI, RLWIMI8, 1007 RLWNM, RLWNM8, 1008 SLD, 1009 SLW, SLW8, 1010 SRAD, 1011 SRAW, 1012 SRD, 1013 SRW, SRW8, 1014 SUBF, SUBF8, 1015 SUBF8_rec, SUBF_rec, 1016 SUBFE, SUBFE8, 1017 SUBFE8O, SUBFEO, 1018 SUBF8O, SUBFO, 1019 VADDUBM, 1020 VADDUDM, 1021 VADDUHM, 1022 VADDUWM, 1023 VAND, 1024 VANDC, 1025 VCMPEQUB, 1026 VCMPEQUD, 1027 VCMPEQUH, 1028 VCMPEQUW, 1029 VCMPGTSB, 1030 VCMPGTSD, 1031 VCMPGTSH, 1032 VCMPGTSW, 1033 VCMPGTUB, 1034 VCMPGTUD, 1035 VCMPGTUH, 1036 VCMPGTUW, 1037 VCMPNEB, 1038 VCMPNEH, 1039 VCMPNEW, 1040 VCMPNEZB, 1041 VCMPNEZH, 1042 VCMPNEZW, 1043 VEQV, 1044 VMAXSB, 1045 VMAXSD, 1046 VMAXSH, 1047 VMAXSW, 1048 VMAXUB, 1049 VMAXUD, 1050 VMAXUH, 1051 VMAXUW, 1052 VMINSB, 1053 VMINSD, 1054 VMINSH, 1055 VMINSW, 1056 VMINUB, 1057 VMINUD, 1058 VMINUH, 1059 VMINUW, 1060 VMRGEW, 1061 VMRGOW, 1062 VNAND, 1063 VNOR, 1064 VOR, 1065 VORC, 1066 VRLB, 1067 VRLD, 1068 VRLDNM, 1069 VRLH, 1070 VRLW, 1071 VRLWNM, 1072 VSLB, 1073 VSLD, 1074 VSLH, 1075 VSLW, 1076 VSRAB, 1077 VSRAD, 1078 VSRAH, 1079 VSRAW, 1080 VSRB, 1081 VSRD, 1082 VSRH, 1083 VSRW, 1084 VSUBUBM, 1085 VSUBUDM, 1086 VSUBUHM, 1087 VSUBUWM, 1088 VXOR, V_SET0, V_SET0B, V_SET0H, 1089 XOR, XOR8, 1090 XOR8_rec, XOR_rec, 1091 XSCPSGNDP, 1092 XSCPSGNQP, 1093 XSIEXPDP, 1094 XSIEXPQP, 1095 XVCPSGNDP, 1096 XVCPSGNSP, 1097 XVIEXPDP, 1098 XVIEXPSP, 1099 XXLAND, 1100 XXLANDC, 1101 XXLEQV, XXLEQVOnes, 1102 XXLNAND, 1103 XXLNOR, 1104 XXLOR, XXLORf, 1105 XXLORC, 1106 XXLXOR, XXLXORdpz, XXLXORspz, XXLXORz 1107)>; 1108 1109// 3 Cycles ALU operations, 3 input operands 1110def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read, P10FX_Read], 1111 (instrs 1112 ISEL, ISEL8, 1113 VRLDMI, 1114 VRLWMI, 1115 VSEL, 1116 XXSEL 1117)>; 1118 1119// Single crack instructions 1120// 3 Cycles ALU operations, 0 input operands 1121def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1122 (instrs 1123 MFFS, 1124 MFFS_rec, 1125 MFFSCDRNI, 1126 MFFSCRNI, 1127 MFFSL, 1128 MFVSCR, 1129 MTFSB0 1130)>; 1131 1132// Single crack instructions 1133// 3 Cycles ALU operations, 1 input operands 1134def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read], 1135 (instrs 1136 ADDIC_rec, 1137 ADDME8_rec, ADDME_rec, 1138 ADDME8O_rec, ADDMEO_rec, 1139 ADDZE8_rec, ADDZE_rec, 1140 ADDZE8O_rec, ADDZEO_rec, 1141 MCRFS, 1142 MFFSCDRN, 1143 MFFSCRN, 1144 MTVSCR, 1145 NEG8O_rec, NEGO_rec, 1146 SUBFME8_rec, SUBFME_rec, 1147 SUBFME8O_rec, SUBFMEO_rec, 1148 SUBFZE8_rec, SUBFZE_rec, 1149 SUBFZE8O_rec, SUBFZEO_rec 1150)>; 1151 1152// Single crack instructions 1153// 3 Cycles ALU operations, 2 input operands 1154def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1155 (instrs 1156 ADDE8_rec, ADDE_rec, 1157 ADDE8O_rec, ADDEO_rec, 1158 ADD4O_rec, ADD8O_rec, 1159 SUBFE8_rec, SUBFE_rec, 1160 SUBFE8O_rec, SUBFEO_rec, 1161 SUBF8O_rec, SUBFO_rec 1162)>; 1163 1164// 2-way crack instructions 1165// 3 Cycles ALU operations, and 4 Cycles ALU2 operations, 2 input operands 1166def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_F2_4C, P10W_DISP_ANY], 1167 (instrs 1168 ADDG6S, ADDG6S8 1169)>; 1170 1171// 2-way crack instructions 1172// 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands 1173def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1174 (instrs 1175 HRFID, 1176 MFFSCE, 1177 MTFSB1, 1178 MTFSFI, MTFSFIb, 1179 MTFSFI_rec, 1180 RFEBB, 1181 RFID, 1182 SC, 1183 STOP 1184)>; 1185 1186// 2-way crack instructions 1187// 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands 1188def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read], 1189 (instrs 1190 FABSD_rec, FABSS_rec, 1191 FMR_rec, 1192 FNABSD_rec, FNABSS_rec, 1193 FNEGD_rec, FNEGS_rec, 1194 MTFSF, MTFSFb, 1195 MTFSF_rec 1196)>; 1197 1198// 2-way crack instructions 1199// 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1200def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1201 (instrs 1202 ADDC, ADDC8, 1203 ADDC8_rec, ADDC_rec, 1204 ADDC8O, ADDCO, 1205 FCPSGND_rec, FCPSGNS_rec, 1206 SUBFC, SUBFC8, 1207 SUBFC8_rec, SUBFC_rec, 1208 SUBFC8O, SUBFCO 1209)>; 1210 1211// 4-way crack instructions 1212// 3 Cycles ALU operations, 3 Cycles ALU operations, 3 Cycles ALU operations, and 3 Cycles ALU operations, 2 input operands 1213def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read], 1214 (instrs 1215 ADDC8O_rec, ADDCO_rec, 1216 SUBFC8O_rec, SUBFCO_rec 1217)>; 1218 1219// 2-way crack instructions 1220// 3 Cycles ALU operations, and 4 Cycles Permute operations, 1 input operands 1221def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_PM_4C, P10W_DISP_ANY], 1222 (instrs 1223 VSTRIBL_rec, 1224 VSTRIBR_rec, 1225 VSTRIHL_rec, 1226 VSTRIHR_rec 1227)>; 1228 1229// 2-way crack instructions 1230// 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands 1231def : InstRW<[P10W_FX_3C, P10W_DISP_PAIR, P10W_FX_3C, P10FX_Read], 1232 (instrs 1233 MTCRF, MTCRF8 1234)>; 1235 1236// 6 Cycles Load operations, 0 input operands 1237def : InstRW<[P10W_LD_6C, P10W_DISP_ANY], 1238 (instrs 1239 LBZ, LBZ8, 1240 LD, LDtoc, LDtocBA, LDtocCPT, LDtocJTI, LDtocL, SPILLTOVSR_LD, 1241 DFLOADf32, DFLOADf64, LFD, 1242 LHA, LHA8, 1243 LHZ, LHZ8, 1244 LWA, LWA_32, 1245 LWZ, LWZ8, LWZtoc, LWZtocL, 1246 LXSD, 1247 LXV 1248)>; 1249 1250// 6 Cycles Load operations, 1 input operands 1251def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1252 (instrs 1253 LXVL, 1254 LXVLL 1255)>; 1256 1257// 6 Cycles Load operations, 2 input operands 1258def : InstRW<[P10W_LD_6C, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1259 (instrs 1260 DCBT, 1261 DCBTST, 1262 ICBT, 1263 LBZX, LBZX8, LBZXTLS, LBZXTLS_, LBZXTLS_32, 1264 LDBRX, 1265 LDX, LDXTLS, LDXTLS_, SPILLTOVSR_LDX, 1266 LFDX, LFDXTLS, LFDXTLS_, XFLOADf32, XFLOADf64, 1267 LFIWAX, LIWAX, 1268 LFIWZX, LIWZX, 1269 LHAX, LHAX8, LHAXTLS, LHAXTLS_, LHAXTLS_32, 1270 LHBRX, LHBRX8, 1271 LHZX, LHZX8, LHZXTLS, LHZXTLS_, LHZXTLS_32, 1272 LVEBX, 1273 LVEHX, 1274 LVEWX, 1275 LVX, 1276 LVXL, 1277 LWAX, LWAXTLS, LWAXTLS_, LWAXTLS_32, LWAX_32, 1278 LWBRX, LWBRX8, 1279 LWZX, LWZX8, LWZXTLS, LWZXTLS_, LWZXTLS_32, 1280 LXSDX, 1281 LXSIBZX, 1282 LXSIHZX, 1283 LXSIWAX, 1284 LXSIWZX, 1285 LXVB16X, 1286 LXVD2X, 1287 LXVDSX, 1288 LXVH8X, 1289 LXVRBX, 1290 LXVRDX, 1291 LXVRHX, 1292 LXVRWX, 1293 LXVW4X, 1294 LXVWSX, 1295 LXVX 1296)>; 1297 1298// 2-way crack instructions 1299// 6 Cycles Load operations, and 13 Cycles Decimal Floating Point operations, 1 input operands 1300def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DF_13C, P10W_DISP_ANY], 1301 (instrs 1302 HASHCHK, HASHCHK8, 1303 HASHCHKP, HASHCHKP8 1304)>; 1305 1306// Single crack instructions 1307// 6 Cycles Load operations, 0 input operands 1308def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY], 1309 (instrs 1310 DARN, 1311 SLBIA 1312)>; 1313 1314// Single crack instructions 1315// 6 Cycles Load operations, 1 input operands 1316def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read], 1317 (instrs 1318 MTSPR, MTSPR8, MTSR, MTUDSCR, MTVRSAVE, MTVRSAVEv, 1319 SLBFEE_rec, 1320 SLBIE, 1321 SLBMFEE, 1322 SLBMFEV 1323)>; 1324 1325// Single crack instructions 1326// 6 Cycles Load operations, 2 input operands 1327def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_DISP_ANY, P10LD_Read, P10LD_Read], 1328 (instrs 1329 LBARX, LBARXL, 1330 LBZCIX, 1331 LDARX, LDARXL, 1332 LDCIX, 1333 LHARX, LHARXL, 1334 LHZCIX, 1335 LWARX, LWARXL, 1336 LWZCIX 1337)>; 1338 1339// Expand instructions 1340// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 0 input operands 1341def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY], 1342 (instrs 1343 LMW 1344)>; 1345 1346// Expand instructions 1347// 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1348def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10LD_Read], 1349 (instrs 1350 LSWI 1351)>; 1352 1353// 2-way crack instructions 1354// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1355def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_SX_3C, P10W_DISP_ANY], 1356 (instrs 1357 LBZU, LBZU8, 1358 LDU, 1359 LFDU, 1360 LHAU, LHAU8, 1361 LHZU, LHZU8, 1362 LWZU, LWZU8 1363)>; 1364 1365// 2-way crack instructions 1366// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 2 input operands 1367def : InstRW<[P10W_LD_6C, P10W_DISP_EVEN, P10W_SX_3C, P10W_DISP_ANY], 1368 (instrs 1369 LBZUX, LBZUX8, 1370 LDUX, 1371 LFDUX, 1372 LHAUX, LHAUX8, 1373 LHZUX, LHZUX8, 1374 LWAUX, 1375 LWZUX, LWZUX8 1376)>; 1377 1378// 6 Cycles Load operations, 0 input operands 1379def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR], 1380 (instrs 1381 PLBZ, PLBZ8, PLBZ8pc, PLBZpc, 1382 PLD, PLDpc, 1383 PLFD, PLFDpc, 1384 PLFS, PLFSpc, 1385 PLHA, PLHA8, PLHA8pc, PLHApc, 1386 PLHZ, PLHZ8, PLHZ8pc, PLHZpc, 1387 PLWA, PLWA8, PLWA8pc, PLWApc, 1388 PLWZ, PLWZ8, PLWZ8pc, PLWZpc, 1389 PLXSD, PLXSDpc, 1390 PLXSSP, PLXSSPpc, 1391 PLXV, PLXVpc, 1392 PLXVP, PLXVPpc 1393)>; 1394 1395// 2-way crack instructions 1396// 6 Cycles Load operations, and 4 Cycles ALU2 operations, 0 input operands 1397def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C], 1398 (instrs 1399 LFS, 1400 LXSSP 1401)>; 1402 1403// 2-way crack instructions 1404// 6 Cycles Load operations, and 4 Cycles ALU2 operations, 2 input operands 1405def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C], 1406 (instrs 1407 LFSX, LFSXTLS, LFSXTLS_, 1408 LXSSPX 1409)>; 1410 1411// 4-way crack instructions 1412// 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 0 input operands 1413def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C, P10W_SX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY], 1414 (instrs 1415 LFSU 1416)>; 1417 1418// 4-way crack instructions 1419// 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 2 input operands 1420def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_F2_4C, P10W_SX_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY], 1421 (instrs 1422 LFSUX 1423)>; 1424 1425// 2-way crack instructions 1426// 6 Cycles Load operations, and 6 Cycles Load operations, 1 input operands 1427def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read], 1428 (instrs 1429 TLBIEL 1430)>; 1431 1432// 2-way crack instructions 1433// 6 Cycles Load operations, and 6 Cycles Load operations, 2 input operands 1434def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_LD_6C, P10W_DISP_PAIR, P10LD_Read, P10LD_Read], 1435 (instrs 1436 SLBMTE 1437)>; 1438 1439// 2-way crack instructions 1440// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1441def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C], 1442 (instrs 1443 LXVP 1444)>; 1445 1446// 2-way crack instructions 1447// 6 Cycles Load operations, and 3 Cycles Simple Fixed-point (SFX) operations, 2 input operands 1448def : InstRW<[P10W_LD_6C, P10W_DISP_PAIR, P10W_SX_3C], 1449 (instrs 1450 LXVPX 1451)>; 1452 1453// Single crack instructions 1454// 13 Cycles Unknown operations, 1 input operands 1455def : InstRW<[P10W_MFL_13C, P10W_DISP_EVEN, P10W_DISP_ANY], 1456 (instrs 1457 MFSPR, MFSPR8, MFSR, MFTB8, MFUDSCR, MFVRSAVE, MFVRSAVEv 1458)>; 1459 1460// 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands 1461def : InstRW<[P10W_MM_10C, P10W_DISP_ANY], 1462 (instrs 1463 XXSETACCZ 1464)>; 1465 1466// 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1467def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read], 1468 (instrs 1469 XVBF16GER2, 1470 XVF16GER2, 1471 XVF32GER, 1472 XVF64GER, 1473 XVI16GER2, 1474 XVI16GER2S, 1475 XVI4GER8, 1476 XVI8GER4 1477)>; 1478 1479// 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1480def : InstRW<[P10W_MM_10C, P10W_DISP_ANY, P10MM_Read, P10MM_Read, P10MM_Read], 1481 (instrs 1482 XVBF16GER2NN, 1483 XVBF16GER2NP, 1484 XVBF16GER2PN, 1485 XVBF16GER2PP, 1486 XVF16GER2NN, 1487 XVF16GER2NP, 1488 XVF16GER2PN, 1489 XVF16GER2PP, 1490 XVF32GERNN, 1491 XVF32GERNP, 1492 XVF32GERPN, 1493 XVF32GERPP, 1494 XVF64GERNN, 1495 XVF64GERNP, 1496 XVF64GERPN, 1497 XVF64GERPP, 1498 XVI16GER2PP, 1499 XVI16GER2SPP, 1500 XVI4GER8PP, 1501 XVI8GER4PP, 1502 XVI8GER4SPP 1503)>; 1504 1505// 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1506def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read], 1507 (instrs 1508 PMXVBF16GER2, 1509 PMXVF16GER2, 1510 PMXVF32GER, 1511 PMXVF64GER, 1512 PMXVI16GER2, 1513 PMXVI16GER2S, 1514 PMXVI4GER8, 1515 PMXVI8GER4 1516)>; 1517 1518// 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1519def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10MM_Read, P10MM_Read, P10MM_Read], 1520 (instrs 1521 PMXVBF16GER2NN, 1522 PMXVBF16GER2NP, 1523 PMXVBF16GER2PN, 1524 PMXVBF16GER2PP, 1525 PMXVF16GER2NN, 1526 PMXVF16GER2NP, 1527 PMXVF16GER2PN, 1528 PMXVF16GER2PP, 1529 PMXVF32GERNN, 1530 PMXVF32GERNP, 1531 PMXVF32GERPN, 1532 PMXVF32GERPP, 1533 PMXVF64GERNN, 1534 PMXVF64GERNP, 1535 PMXVF64GERPN, 1536 PMXVF64GERPP, 1537 PMXVI16GER2PP, 1538 PMXVI16GER2SPP, 1539 PMXVI4GER8PP, 1540 PMXVI8GER4PP, 1541 PMXVI8GER4SPP 1542)>; 1543 1544// 2-way crack instructions 1545// 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1546def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1547 (instrs 1548 XXMTACC 1549)>; 1550 1551// 4-way crack instructions 1552// 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1553def : InstRW<[P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C, P10W_MM_10C, P10W_DISP_PAIR, P10W_FX_3C], 1554 (instrs 1555 XXMFACC 1556)>; 1557 1558// 5 Cycles GPR Multiply operations, 1 input operands 1559def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read], 1560 (instrs 1561 MULLI, MULLI8 1562)>; 1563 1564// 5 Cycles GPR Multiply operations, 2 input operands 1565def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read], 1566 (instrs 1567 MULHD, 1568 MULHDU, 1569 MULHW, 1570 MULHWU, 1571 MULLD, 1572 MULLDO, 1573 MULLW, 1574 MULLWO, 1575 VMULHSD, 1576 VMULHUD, 1577 VMULLD 1578)>; 1579 1580// 5 Cycles GPR Multiply operations, 3 input operands 1581def : InstRW<[P10W_MU_5C, P10W_DISP_ANY, P10MU_Read, P10MU_Read, P10MU_Read], 1582 (instrs 1583 MADDHD, 1584 MADDHDU, 1585 MADDLD, MADDLD8 1586)>; 1587 1588// 2-way crack instructions 1589// 5 Cycles GPR Multiply operations, and 3 Cycles ALU operations, 2 input operands 1590def : InstRW<[P10W_MU_5C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1591 (instrs 1592 MULHD_rec, 1593 MULHDU_rec, 1594 MULHW_rec, 1595 MULHWU_rec, 1596 MULLD_rec, 1597 MULLDO_rec, 1598 MULLW_rec, 1599 MULLWO_rec 1600)>; 1601 1602// 4 Cycles Permute operations, 0 input operands 1603def : InstRW<[P10W_PM_4C, P10W_DISP_ANY], 1604 (instrs 1605 LXVKQ, 1606 VSPLTISB, 1607 VSPLTISH, 1608 VSPLTISW, V_SETALLONES, V_SETALLONESB, V_SETALLONESH, 1609 XXSPLTIB 1610)>; 1611 1612// 4 Cycles Permute operations, 1 input operands 1613def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read], 1614 (instrs 1615 BRD, 1616 BRH, BRH8, 1617 BRW, BRW8, 1618 MFVSRLD, 1619 MTVSRWS, 1620 VCLZLSBB, 1621 VCTZLSBB, 1622 VEXTRACTD, 1623 VEXTRACTUB, 1624 VEXTRACTUH, 1625 VEXTRACTUW, 1626 VGBBD, 1627 VINSERTD, 1628 VINSERTW, 1629 VPRTYBQ, 1630 VSPLTB, VSPLTBs, 1631 VSPLTH, VSPLTHs, 1632 VSPLTW, 1633 VSTRIBL, 1634 VSTRIBR, 1635 VSTRIHL, 1636 VSTRIHR, 1637 VUPKHPX, 1638 VUPKHSB, 1639 VUPKHSH, 1640 VUPKHSW, 1641 VUPKLPX, 1642 VUPKLSB, 1643 VUPKLSH, 1644 VUPKLSW, 1645 XVCVBF16SPN, 1646 XXBRD, 1647 XXBRH, 1648 XXBRQ, 1649 XXBRW, 1650 XXEXTRACTUW, 1651 XXGENPCVDM, 1652 XXGENPCVHM, 1653 XXGENPCVWM, 1654 XXSPLTW, XXSPLTWs 1655)>; 1656 1657// 4 Cycles Permute operations, 2 input operands 1658def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read], 1659 (instrs 1660 BPERMD, 1661 LVSL, 1662 LVSR, 1663 MTVSRDD, 1664 VBPERMD, 1665 VBPERMQ, 1666 VCLRLB, 1667 VCLRRB, 1668 VEXTUBLX, 1669 VEXTUBRX, 1670 VEXTUHLX, 1671 VEXTUHRX, 1672 VEXTUWLX, 1673 VEXTUWRX, 1674 VINSD, 1675 VINSERTB, 1676 VINSERTH, 1677 VINSW, 1678 VMRGHB, 1679 VMRGHH, 1680 VMRGHW, 1681 VMRGLB, 1682 VMRGLH, 1683 VMRGLW, 1684 VPKPX, 1685 VPKSDSS, 1686 VPKSDUS, 1687 VPKSHSS, 1688 VPKSHUS, 1689 VPKSWSS, 1690 VPKSWUS, 1691 VPKUDUM, 1692 VPKUDUS, 1693 VPKUHUM, 1694 VPKUHUS, 1695 VPKUWUM, 1696 VPKUWUS, 1697 VSL, 1698 VSLDBI, 1699 VSLDOI, 1700 VSLO, 1701 VSLV, 1702 VSR, 1703 VSRDBI, 1704 VSRO, 1705 VSRV, 1706 XXINSERTW, 1707 XXMRGHW, 1708 XXMRGLW, 1709 XXPERMDI, XXPERMDIs, 1710 XXSLDWI, XXSLDWIs 1711)>; 1712 1713// 4 Cycles Permute operations, 3 input operands 1714def : InstRW<[P10W_PM_4C, P10W_DISP_ANY, P10PM_Read, P10PM_Read, P10PM_Read], 1715 (instrs 1716 VEXTDDVLX, 1717 VEXTDDVRX, 1718 VEXTDUBVLX, 1719 VEXTDUBVRX, 1720 VEXTDUHVLX, 1721 VEXTDUHVRX, 1722 VEXTDUWVLX, 1723 VEXTDUWVRX, 1724 VINSBLX, 1725 VINSBRX, 1726 VINSBVLX, 1727 VINSBVRX, 1728 VINSDLX, 1729 VINSDRX, 1730 VINSHLX, 1731 VINSHRX, 1732 VINSHVLX, 1733 VINSHVRX, 1734 VINSWLX, 1735 VINSWRX, 1736 VINSWVLX, 1737 VINSWVRX, 1738 VPERM, 1739 VPERMR, 1740 VPERMXOR, 1741 XXPERM, 1742 XXPERMR 1743)>; 1744 1745// 2-way crack instructions 1746// 4 Cycles Permute operations, and 7 Cycles VMX Multiply operations, 2 input operands 1747def : InstRW<[P10W_PM_4C, P10W_DISP_EVEN, P10W_vMU_7C, P10W_DISP_ANY], 1748 (instrs 1749 VSUMSWS 1750)>; 1751 1752// 4 Cycles Permute operations, 0 input operands 1753def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR], 1754 (instrs 1755 XXSPLTIDP, 1756 XXSPLTIW 1757)>; 1758 1759// 4 Cycles Permute operations, 1 input operands 1760def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read], 1761 (instrs 1762 XXSPLTI32DX 1763)>; 1764 1765// 4 Cycles Permute operations, 3 input operands 1766def : InstRW<[P10W_PM_4C, P10W_DISP_PAIR, P10PM_Read, P10PM_Read, P10PM_Read], 1767 (instrs 1768 XXBLENDVB, 1769 XXBLENDVD, 1770 XXBLENDVH, 1771 XXBLENDVW, 1772 XXEVAL, 1773 XXPERMX 1774)>; 1775 1776// 3 Cycles Store operations, 1 input operands 1777def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read], 1778 (instrs 1779 PSTXVP, PSTXVPpc, 1780 STB, STB8, 1781 STBU, STBU8, 1782 SPILLTOVSR_ST, STD, 1783 STDU, 1784 DFSTOREf32, DFSTOREf64, STFD, 1785 STFDU, 1786 STFS, 1787 STFSU, 1788 STH, STH8, 1789 STHU, STHU8, 1790 STW, STW8, 1791 STWU, STWU8, 1792 STXSD, 1793 STXSSP, 1794 STXV 1795)>; 1796 1797// 3 Cycles Store operations, 2 input operands 1798def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1799 (instrs 1800 CP_COPY, CP_COPY8, 1801 DCBF, 1802 DCBST, 1803 DCBZ, 1804 ICBI, 1805 STXVL, 1806 STXVLL 1807)>; 1808 1809// 3 Cycles Store operations, 3 input operands 1810def : InstRW<[P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1811 (instrs 1812 STBUX, STBUX8, 1813 STBX, STBX8, STBXTLS, STBXTLS_, STBXTLS_32, 1814 STDBRX, 1815 STDUX, 1816 SPILLTOVSR_STX, STDX, STDXTLS, STDXTLS_, 1817 STFDUX, 1818 STFDX, STFDXTLS, STFDXTLS_, 1819 STFIWX, STIWX, 1820 STFSUX, 1821 STFSX, STFSXTLS, STFSXTLS_, 1822 STHBRX, 1823 STHUX, STHUX8, 1824 STHX, STHX8, STHXTLS, STHXTLS_, STHXTLS_32, 1825 STVEBX, 1826 STVEHX, 1827 STVEWX, 1828 STVX, 1829 STVXL, 1830 STWBRX, 1831 STWUX, STWUX8, 1832 STWX, STWX8, STWXTLS, STWXTLS_, STWXTLS_32, 1833 STXSDX, 1834 STXSIBX, STXSIBXv, 1835 STXSIHX, STXSIHXv, 1836 STXSIWX, 1837 STXSSPX, 1838 STXVB16X, 1839 STXVD2X, 1840 STXVH8X, 1841 STXVRBX, 1842 STXVRDX, 1843 STXVRHX, 1844 STXVRWX, 1845 STXVW4X, 1846 STXVX 1847)>; 1848 1849// Single crack instructions 1850// 3 Cycles Store operations, 0 input operands 1851def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1852 (instrs 1853 EnforceIEIO, 1854 MSGSYNC, 1855 SLBSYNC, 1856 TLBSYNC 1857)>; 1858 1859// Single crack instructions 1860// 3 Cycles Store operations, 2 input operands 1861def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1862 (instrs 1863 CP_PASTE8_rec, CP_PASTE_rec, 1864 SLBIEG, 1865 TLBIE 1866)>; 1867 1868// Single crack instructions 1869// 3 Cycles Store operations, 3 input operands 1870def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read, P10ST_Read], 1871 (instrs 1872 STBCIX, 1873 STBCX, 1874 STDCIX, 1875 STDCX, 1876 STHCIX, 1877 STHCX, 1878 STWCIX, 1879 STWCX 1880)>; 1881 1882// 2-way crack instructions 1883// 3 Cycles Store operations, and 3 Cycles ALU operations, 0 input operands 1884def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 1885 (instrs 1886 ISYNC, 1887 SYNCP10, 1888 SYNC 1889)>; 1890 1891// Expand instructions 1892// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operations, 6 Cycles Load operations, and 3 Cycles Store operations, 1 input operands 1893def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_FX_3C, P10W_DISP_ANY, P10W_LD_6C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1894 (instrs 1895 LDAT, 1896 LWAT 1897)>; 1898 1899// 4-way crack instructions 1900// 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1901def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY], 1902 (instrs 1903 STDAT, 1904 STWAT 1905)>; 1906 1907// Expand instructions 1908// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 1 input operands 1909def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read], 1910 (instrs 1911 STMW 1912)>; 1913 1914// Expand instructions 1915// 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles Store operations, 2 input operands 1916def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10W_ST_3C, P10W_DISP_ANY, P10ST_Read, P10ST_Read], 1917 (instrs 1918 STSWI 1919)>; 1920 1921// 3 Cycles Store operations, 1 input operands 1922def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10ST_Read], 1923 (instrs 1924 PSTB, PSTB8, PSTB8pc, PSTBpc, 1925 PSTD, PSTDpc, 1926 PSTFD, PSTFDpc, 1927 PSTFS, PSTFSpc, 1928 PSTH, PSTH8, PSTH8pc, PSTHpc, 1929 PSTW, PSTW8, PSTW8pc, PSTWpc, 1930 PSTXSD, PSTXSDpc, 1931 PSTXSSP, PSTXSSPpc, 1932 PSTXV, PSTXVpc 1933)>; 1934 1935// 2-way crack instructions 1936// 3 Cycles Store operations, and 3 Cycles Store operations, 1 input operands 1937def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10W_ST_3C, P10ST_Read], 1938 (instrs 1939 STXVP 1940)>; 1941 1942// 2-way crack instructions 1943// 3 Cycles Store operations, and 3 Cycles Store operations, 3 input operands 1944def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10W_ST_3C, P10ST_Read, P10ST_Read, P10ST_Read], 1945 (instrs 1946 STXVPX 1947)>; 1948 1949// FIXME - Miss scheduling information from datasheet 1950// Temporary set it as 1 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1951def : InstRW<[P10W_SX, P10W_DISP_ANY], 1952 (instrs 1953 ATTN, 1954 CP_ABORT, 1955 CRNOT, 1956 DCBA, 1957 DCBI, 1958 DCBZL, 1959 DCCCI, 1960 ICBLC, 1961 ICBLQ, 1962 ICBTLS, 1963 ICCCI, 1964 LA, LA8, 1965 MFDCR, 1966 MFPMR, 1967 MFSRIN, 1968 MSYNC, 1969 MTDCR, 1970 MTPMR, 1971 MTSRIN, 1972 NAP, 1973 TLBIA, 1974 TLBLD, 1975 TLBLI, 1976 TLBRE2, 1977 TLBSX2, 1978 TLBSX2D, 1979 TLBWE2 1980)>; 1981 1982// Single crack instructions 1983// 3 Cycles Simple Fixed-point (SFX) operations, 0 input operands 1984def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY], 1985 (instrs 1986 CLRBHRB, 1987 MFBHRBE, 1988 MFMSR, 1989 MFTB 1990)>; 1991 1992// Single crack instructions 1993// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 1994def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10SX_Read], 1995 (instrs 1996 MTMSR, 1997 MTMSRD 1998)>; 1999 2000// 2-way crack instructions 2001// 3 Cycles Simple Fixed-point (SFX) operations, and 3 Cycles ALU operations, 0 input operands 2002def : InstRW<[P10W_SX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY], 2003 (instrs 2004 ADDPCIS 2005)>; 2006 2007// 3 Cycles Simple Fixed-point (SFX) operations, 1 input operands 2008def : InstRW<[P10W_SX_3C, P10W_DISP_PAIR, P10SX_Read], 2009 (instrs 2010 PADDI, PADDI8, PADDI8pc, PADDIpc, PLI, PLI8 2011)>; 2012 2013// 7 Cycles VMX Multiply operations, 2 input operands 2014def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read], 2015 (instrs 2016 VMULESB, 2017 VMULESD, 2018 VMULESH, 2019 VMULESW, 2020 VMULEUB, 2021 VMULEUD, 2022 VMULEUH, 2023 VMULEUW, 2024 VMULHSW, 2025 VMULHUW, 2026 VMULOSB, 2027 VMULOSD, 2028 VMULOSH, 2029 VMULOSW, 2030 VMULOUB, 2031 VMULOUD, 2032 VMULOUH, 2033 VMULOUW, 2034 VMULUWM, 2035 VSUM2SWS, 2036 VSUM4SBS, 2037 VSUM4SHS, 2038 VSUM4UBS 2039)>; 2040 2041// 7 Cycles VMX Multiply operations, 3 input operands 2042def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read, P10vMU_Read], 2043 (instrs 2044 VMHADDSHS, 2045 VMHRADDSHS, 2046 VMLADDUHM, 2047 VMSUMCUD, 2048 VMSUMMBM, 2049 VMSUMSHM, 2050 VMSUMSHS, 2051 VMSUMUBM, 2052 VMSUMUDM, 2053 VMSUMUHM, 2054 VMSUMUHS 2055)>; 2056 2057