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/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DTargetOpcodes.def9 // This file defines the target independent instruction opcodes.
27 /// Every instruction defined here must also appear in Target.td.
37 /// KILL - This instruction is a noop that is used only to adjust the
42 /// EXTRACT_SUBREG - This instruction takes two operands: a register
48 /// INSERT_SUBREG - This instruction takes three operands: a register that
60 /// The result of this instruction is the value of the second operand inserted
63 /// first operand. This instruction just communicates information; No code
65 /// This is typically used after an instruction where the write to a subregister
69 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
71 /// used between instruction selection and MachineInstr creation, before
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DLeonFeatures.td17 //support to casa instruction; for leon3 subtarget only
31 //support to casa instruction; for leon3 subtarget only
36 "Enable CASA instruction for LEON3 and LEON4 processors"
43 …m fix: Insert a NOP instruction after every single-cycle load instruction when the next instructio…
/freebsd/contrib/llvm-project/lldb/include/lldb/Core/
H A DEmulateInstruction.h331 void Dump(Stream &s, EmulateInstruction *instruction) const;
334 typedef size_t (*ReadMemoryCallback)(EmulateInstruction *instruction,
339 typedef size_t (*WriteMemoryCallback)(EmulateInstruction *instruction,
344 typedef bool (*ReadRegisterCallback)(EmulateInstruction *instruction,
349 typedef bool (*WriteRegisterCallback)(EmulateInstruction *instruction,
444 static size_t ReadMemoryFrame(EmulateInstruction *instruction, void *baton,
448 static size_t WriteMemoryFrame(EmulateInstruction *instruction, void *baton,
452 static bool ReadRegisterFrame(EmulateInstruction *instruction, void *baton,
456 static bool WriteRegisterFrame(EmulateInstruction *instruction, void *baton,
461 static size_t ReadMemoryDefault(EmulateInstruction *instruction, void *baton,
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetItinerary.td10 // which should be implemented by each target that uses instruction
12 // tables for each instruction class. They are most appropriate for
22 // during scheduling and has an affect instruction order based on availability
43 // the execution of an instruction. Cycles represents the number of
67 // required to complete an instruction. Itineraries are represented as lists of
68 // instruction stages.
72 // Instruction itinerary classes - These values represent 'named' instruction
74 // instructions across chip sets. An instruction uses the same itinerary class
76 // instruction information.
83 // instruction itinerary class (name) to its itinerary data.
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H A DTarget.td200 // some registers require larger instruction encodings, by the RISC-V target,
282 // meaning it takes a single instruction to perform the copying. A negative
299 // model instruction operand constraints, and should have isAllocatable = 0.
514 /// Specifies a Subtarget feature that this instruction is deprecated on.
519 /// A custom predicate used to determine if an instruction is
536 // Size of encoded instruction.
539 // The "namespace" in which this instruction exists, on targets like ARM
548 // Is the instruction decoder method able to completely determine if the
549 // given instruction is valid or not. If the TableGen definition of the
550 // instruction specifies bitpattern A??B where A and B are static bits, the
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/freebsd/contrib/llvm-project/lldb/source/Plugins/UnwindAssembly/InstEmulation/
H A DUnwindAssemblyInstEmulation.h78 ReadMemory(lldb_private::EmulateInstruction *instruction, void *baton,
83 WriteMemory(lldb_private::EmulateInstruction *instruction, void *baton,
87 static bool ReadRegister(lldb_private::EmulateInstruction *instruction,
93 WriteRegister(lldb_private::EmulateInstruction *instruction, void *baton,
105 size_t WriteMemory(lldb_private::EmulateInstruction *instruction,
109 bool ReadRegister(lldb_private::EmulateInstruction *instruction,
113 bool WriteRegister(lldb_private::EmulateInstruction *instruction,
H A DUnwindAssemblyInstEmulation.cpp379 EmulateInstruction *instruction, void *baton, in ReadMemory() argument
390 context.Dump(strm, instruction); in ReadMemory()
398 EmulateInstruction *instruction, void *baton, in WriteMemory() argument
403 ->WriteMemory(instruction, context, addr, dst, dst_len); in WriteMemory()
408 EmulateInstruction *instruction, const EmulateInstruction::Context &context, in WriteMemory() argument
411 instruction->GetArchitecture().GetByteOrder(), in WriteMemory()
412 instruction->GetArchitecture().GetAddressByteSize()); in WriteMemory()
423 context.Dump(strm, instruction); in WriteMemory()
478 bool UnwindAssemblyInstEmulation::ReadRegister(EmulateInstruction *instruction, in ReadRegister() argument
485 ->ReadRegister(instruction, reg_info, reg_value); in ReadRegister()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td33 // This class does not depend on the instruction size
69 // For 32 bit extended instruction forms.
99 // Format I instruction class in Mips : <|opcode|imm11|>
114 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
131 // Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
228 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
248 // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
270 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
292 // Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
314 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td9 // This file describes the RISC-V C extension instruction formats.
37 // The immediate value encoding differs for each instruction, so each subclass
39 // The bits Inst{6-2} must be set for each instruction.
52 // The immediate value encoding differs for each instruction, so each subclass
54 // The bits Inst{12-7} must be set for each instruction.
78 // The immediate value encoding differs for each instruction, so each subclass
80 // The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
93 // The immediate value encoding differs for each instruction, so each subclass
95 // The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
160 // The immediate value encoding differs for each instruction, so each subclass
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H A DRISCVInstrInfoVPseudos.td14 /// Overview of our vector instruction pseudos. Many of the instructions
18 /// specific instruction, but the common dimensions are:
49 /// instructions for each actual instruction. Said differently, we encode
50 /// each of the preceding fields which are relevant for a given instruction
722 // The destination vector register group for a masked vector instruction cannot
2403 // For vadc and vsbc, the instruction encoding is reserved if the destination
4603 multiclass VPatUnaryV_V_AnyMask<string intrinsic, string instruction,
4607 def : VPatUnaryAnyMask<intrinsic, instruction, "VM",
4621 multiclass VPatUnaryV_M<string intrinsic, string instruction> {
4624 def : VPatUnaryNoMask<intrinsic, instruction, "
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H A DRISCVInstrInfoZvk.td95 // op vd, vs2 (use vs1 as instruction encoding) where vd is also a source
910 multiclass VPatUnaryV_V_NoMask_Zvk<string intrinsic, string instruction,
913 def : VPatUnaryNoMask_Zvk<intrinsic # "_vv", instruction, "VV",
918 multiclass VPatUnaryV_S_NoMaskVectorCrypto<string intrinsic, string instruction,
922 def : VPatUnaryNoMask_VS_Zvk<intrinsic # "_vs", instruction, "VS",
927 multiclass VPatUnaryV_V_S_NoMask_Zvk<string intrinsic, string instruction,
929 defm : VPatUnaryV_V_NoMask_Zvk<intrinsic, instruction, vtilist>;
930 defm : VPatUnaryV_S_NoMaskVectorCrypto<intrinsic, instruction, vtilist>;
933 multiclass VPatBinaryV_VV_NoMask<string intrinsic, string instruction,
936 def : VPatTernaryNoMaskWithPolicy<intrinsic, instruction, "VV",
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/freebsd/contrib/llvm-project/lld/MachO/Arch/
H A DARM64Common.cpp99 uint32_t instruction = read32le(loc); in relaxGotLoad() local
103 if ((instruction & 0xbfc00000) != 0xb9400000) in relaxGotLoad()
105 assert(((instruction >> 10) & 0xfff) == 0 && in relaxGotLoad()
109 instruction = ((instruction & 0x001fffff) | 0x91000000); in relaxGotLoad()
110 write32le(loc, instruction); in relaxGotLoad()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulationStateARM.h41 ReadPseudoMemory(lldb_private::EmulateInstruction *instruction, void *baton,
46 WritePseudoMemory(lldb_private::EmulateInstruction *instruction, void *baton,
50 static bool ReadPseudoRegister(lldb_private::EmulateInstruction *instruction,
56 WritePseudoRegister(lldb_private::EmulateInstruction *instruction,
/freebsd/contrib/llvm-project/lldb/source/Core/
H A DEmulateInstruction.cpp257 size_t EmulateInstruction::ReadMemoryFrame(EmulateInstruction *instruction, in ReadMemoryFrame() argument
274 size_t EmulateInstruction::WriteMemoryFrame(EmulateInstruction *instruction, in WriteMemoryFrame() argument
292 bool EmulateInstruction::ReadRegisterFrame(EmulateInstruction *instruction, in ReadRegisterFrame() argument
303 bool EmulateInstruction::WriteRegisterFrame(EmulateInstruction *instruction, in WriteRegisterFrame() argument
314 size_t EmulateInstruction::ReadMemoryDefault(EmulateInstruction *instruction, in ReadMemoryDefault() argument
323 context.Dump(strm, instruction); in ReadMemoryDefault()
329 size_t EmulateInstruction::WriteMemoryDefault(EmulateInstruction *instruction, in WriteMemoryDefault() argument
338 context.Dump(strm, instruction); in WriteMemoryDefault()
343 bool EmulateInstruction::ReadRegisterDefault(EmulateInstruction *instruction, in ReadRegisterDefault() argument
359 bool EmulateInstruction::WriteRegisterDefault(EmulateInstruction *instruction, in WriteRegisterDefault() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td20 // SALU instruction formats.
27 // VALU instruction formats.
38 // Memory instruction formats.
52 // LDSDIR instruction format.
55 // VINTERP instruction format.
63 // Whether WQM _must_ be enabled for this instruction.
66 // Whether WQM _must_ be disabled for this instruction.
71 // This is an s_store_dword* instruction that requires a cache flush
77 // instruction size.
84 // Is it possible for this instruction to be atomic?
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DTarget.td10 // SelectionDAG instruction selection patterns (specified in
11 // TargetSelectionDAG.td) when generating GlobalISel instruction selectors.
53 // renders directly to the result instruction without an intermediate node.
58 // The function renders the operand(s) of the matched instruction to
59 // the specified instruction. It should be of the form:
66 // where there is no corresponding instruction to match.
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrFormats.td41 // except for the `AND' instruction (`AAA' = 100), for which the other
45 // `F' determines whether the instruction modifies (1) or does not
85 // The all-0s word is the instruction `R0 <- R0 + 0', which is a no-op.
117 // `DDDI' is as described for the BR instruction.
119 // `F' determines whether the instruction modifies (1) or does not
142 // DDDI is as described in the table for the BR instruction and only used for
143 // the select instruction.
181 // `S' determines whether the instruction is a Load (0) or a Store (1).
182 // Loads appear in Rd one cycle after this instruction executes. If the
183 // following instruction reads Rd, that instruction will be delayed by 1
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td14 // Vector instruction type enum
44 // with 0 meaning the operation is not a surface instruction. For example,
45 // if IsSuld == 2, then the instruction is a suld instruction with vector size
/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_s390xcap.pod13 libcrypto supports z/Architecture instruction set extensions. These
15 When libcrypto is initialized, the bits returned by the STFLE instruction
36 implements the corresponding instruction set extension. Possible values
42 The name of an instruction followed by two 64-bit masks. The part of the
43 environment variable's mask corresponding to the specified instruction is
52 instruction is set to the specified 192-bit mask.
59 The following is a list of significant bits for each instruction. Colon
174 Disables all instruction set extensions which the z196 processor does not implement:
H A DOPENSSL_ia32cap.pod13 OpenSSL supports a range of x86[_64] instruction set extensions. These
15 by processor in EDX:ECX register pair after executing CPUID instruction
26 =item bit #19 denoting availability of CLFLUSH instruction;
43 =item bit #33 denoting availability of PCLMULQDQ instruction;
49 =item bit #54 denoting availability of MOVBE instruction;
51 =item bit #57 denoting AES-NI instruction set extension;
60 =item bit #62 denoting availability of RDRAND instruction;
102 =item bit #64+18 denoting availability of RDSEED instruction;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredicates.td75 // Identify whether an instruction is NEON or floating point
81 // Identify whether an instruction is the 16-bit NEON form based on its result.
87 // Identify whether an instruction is the 128-bit NEON form based on its result.
144 // Identify whether an instruction is an ASIMD
173 // Identify whether an instruction is an ASIMD
194 // Identify whether an instruction is an ASIMD load
199 // Identify whether an instruction is a load
215 // Identify whether an instruction is a store
227 // Identify whether an instruction is a load or
281 // Identify an instruction that effectively transfers a register to another.
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFormats.td13 // Format specifies the encoding used by the instruction. This is part of the
14 // ad-hoc solution used to emit machine instruction encodings by our machine
83 // ImmType - This specifies the immediate type used by an instruction. This is
84 // part of the ad-hoc solution used to emit machine instruction encodings by our
100 // FPFormat - This specifies what form this FP instruction has. This is used by
150 // decode to this instruction. e.g. ANDSS/ANDSD don't
197 // Force the instruction to use REX2/VEX/EVEX encoding.
220 // If this is a pseudo instruction, mark it isCodeGenOnly.
228 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
232 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
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/freebsd/sys/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m421 dnl instruction sets.
29 dnl although the instruction set of 'mips' is a large subset of the
30 dnl instruction set of 'mipsn32'.
33 dnl the instruction sets of 'mipsn32' and 'mips64' are the same.
45 dnl - Speed of execution of the common instruction set is reasonable across
66 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
67 # - 64-bit instruction set, 64-bit pointers, 32-bit 'long': x86_64
69 # - 64-bit instruction set, 32-bit pointers, 32-bit 'long': x86_64-x32.
70 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': i386.
103 # - aarch64 instruction set, 64-bit pointers, 64-bit 'long': arm64.
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFormats.td10 /// WebAssembly instruction format definitions.
15 // We instantiate 2 of these for every actual instruction (register based
42 // Generates both register and stack based versions of one actual instruction.
44 // based version of this instruction, as well as the corresponding asmstr.
53 // Every instruction should want to be based on this multi-class to guarantee
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td13 // A generic AVR instruction.
26 /// A 16-bit AVR instruction.
34 /// a 32-bit AVR instruction.
47 // For example, the ADDW (add wide, as in add 16 bit values) instruction
48 // is defined as a pseudo instruction. In AVRExpandPseudoInsts.cpp,
49 // the instruction is then replaced by two add instructions - one for each byte.
59 // Register / register instruction: <|opcode|ffrd|dddd|rrrr|>
98 // Register / immediate8 instruction: <|opcode|KKKK|dddd|KKKK|>
118 // Register instruction: <|opcode|fffd|dddd|ffff|>
163 // An ST/LD instruction
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