Lines Matching refs:instruction

41 // except for the `AND' instruction (`AAA' = 100), for which the other
45 // `F' determines whether the instruction modifies (1) or does not
85 // The all-0s word is the instruction `R0 <- R0 + 0', which is a no-op.
117 // `DDDI' is as described for the BR instruction.
119 // `F' determines whether the instruction modifies (1) or does not
142 // DDDI is as described in the table for the BR instruction and only used for
143 // the select instruction.
181 // `S' determines whether the instruction is a Load (0) or a Store (1).
182 // Loads appear in Rd one cycle after this instruction executes.  If the
183 // following instruction reads Rd, that instruction will be delayed by 1
193 // The constant is sign-extended for this instruction.
231 // The RRM instruction is identical to the RM (*note RM::.) instruction
235 //    determined in the same way as in the RR instruction (*note RR::.)
296 // The BR instruction is an absolute branch.
297 // The constant is scaled as shown by its position in the instruction word such
322 // If the branch is not taken, the BR instruction is a no-op.  If the branch is
324 // address *after* the processor has executed one more instruction.  That is,
388 // specified by DDDI, as described in the table for the BR instruction.
453 // RM instruction (*note RM::.).
484 //             [Note: here ea is determined as in the RM instruction. ]
490 // `P' and `Q' are used to determine `ea' as in the RM instruction. The