Home
last modified time | relevance | path

Searched refs:i8 (Results 1 – 25 of 236) sorted by relevance

12345678910

/freebsd/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
H A Dtst.signedkeyspos.d50 @i8["cat", (char)-2] = sum(-2);
51 @i8["dog", (char)-2] = sum(-22);
52 @i8["mouse", (char)-2] = sum(-222);
53 @i8["cat", (char)-1] = sum(-1);
54 @i8["dog", (char)-1] = sum(-11);
55 @i8["mouse", (char)-1] = sum(-111);
56 @i8["cat", (char)0] = sum(0);
57 @i8["dog", (char)0] = sum(10);
58 @i8["mouse", (char)0] = sum(100);
59 @i8["cat", (char)1] = sum(1);
[all …]
H A Dtst.signedkeys.d95 @i8[(char)-2] = sum(-2);
96 @i8[(char)-1] = sum(-1);
97 @i8[(char)0] = sum(0);
98 @i8[(char)1] = sum(1);
99 @i8[(char)2] = sum(2);
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp84 return TII->ExpandMOVI(MIB, MVT::i8); in INITIALIZE_PASS()
91 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in INITIALIZE_PASS()
93 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in INITIALIZE_PASS()
98 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in INITIALIZE_PASS()
100 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in INITIALIZE_PASS()
105 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8); in INITIALIZE_PASS()
107 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i8); in INITIALIZE_PASS()
113 MVT::i8); in INITIALIZE_PASS()
116 MVT::i8); in INITIALIZE_PASS()
123 MVT::i8); in INITIALIZE_PASS()
[all …]
H A DM68kCallingConv.td28 CCIfType<[i1], CCPromoteToType<i8>>,
29 CCIfType<[i8], CCAssignToReg<[BD0, BD1]>>,
40 CCIfType<[i1], CCPromoteToType<i8>>,
41 CCIfType<[i8], CCAssignToReg<[BD0, BD1]>>,
68 /// Promote i1/i8/i16 arguments to i32.
69 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
83 /// Promote i1/i8/i16 arguments to i32.
84 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
H A DM68kInstrInfo.td37 /* CCR */ SDTCisVT<1, i8>,
44 /* CCR */ SDTCisVT<1, i8>,
52 /* CCR */ SDTCisVT<1, i8>,
59 /* CCR */ SDTCisVT<0, i8>,
66 /* Cond */ SDTCisVT<3, i8>,
67 /* CCR */ SDTCisVT<4, i8>
72 /* Cond */ SDTCisVT<1, i8>,
73 /* CCR */ SDTCisVT<2, i8>
77 /* BOOL */ SDTCisVT<0, i8>,
78 /* Cond */ SDTCisVT<1, i8>,
[all …]
H A DM68kInstrArithmetic.td319 // t8: i32,i8 = ADD32ab GLOBAL_OFFSET_TABLE, TargetGlobalTLSAddress:i32<ptr @myvar>
561 def : Pat<(sext_inreg i16:$src, i8), (EXT16 $src)>;
563 def : Pat<(sext_inreg i32:$src, i8),
645 // RR i8
646 def : Pat<(sdiv i8:$dst, i8:$opd),
651 def : Pat<(udiv i8:$dst, i8:$opd),
656 def : Pat<(srem i8:$dst, i8:$opd),
661 def : Pat<(urem i8:$dst, i8:$opd),
687 // RI i8
688 def : Pat<(sdiv i8:$dst, Mxi8immSExt8:$opd),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td24 : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
29 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
91 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i8);
108 ~((uint8_t) N->getZExtValue()), SDLoc(N), MVT::i8);
117 def imm_com8 : Operand<i8> { let ParserMatchClass = imm_com8_asmoperand; }
122 uint8_t(N->getZExtValue()) - offset, SDLoc(N), MVT::i8);
127 Log2_32(uint8_t(N->getZExtValue())), SDLoc(N), MVT::i8);
132 Log2_32(uint8_t(~N->getZExtValue())), SDLoc(N), MVT::i8);
219 def imm_ldi8 : Operand<i8> {
224 def imm_port5 : Operand<i8> {
[all …]
H A DAVRISelDAGToDAG.cpp89 Disp = CurDAG->getTargetConstant(0, dl, MVT::i8); in SelectAddr()
128 bool OkI8 = VT == MVT::i8 && RHSC <= 63; in SelectAddr()
133 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i8); in SelectAddr()
160 case MVT::i8: { in selectIndexedLoad()
203 if (VT.SimpleTy == MVT::i8 && Offs == 1 && Bank == 0) in selectIndexedProgMemLoad()
290 if (ImmNode->getValueType(0) != MVT::i8) { in SelectInlineAsmMemoryOperand()
291 Disp = CurDAG->getTargetConstant(ImmNode->getZExtValue(), dl, MVT::i8); in SelectInlineAsmMemoryOperand()
405 SDValue NC = CurDAG->getTargetConstant(ProgMemBank, DL, MVT::i8); in select()
406 auto *NP = CurDAG->getMachineNode(AVR::LDIRdK, DL, MVT::i8, NC); in select()
413 case MVT::i8: in select()
[all …]
H A DAVRISelLowering.cpp40 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); in AVRTargetLowering()
57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); in AVRTargetLowering()
65 setLoadExtAction(N, VT, MVT::i8, Expand); in AVRTargetLowering()
69 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in AVRTargetLowering()
85 setOperationAction(ISD::SRA, MVT::i8, Custom); in AVRTargetLowering()
86 setOperationAction(ISD::SHL, MVT::i8, Custom); in AVRTargetLowering()
87 setOperationAction(ISD::SRL, MVT::i8, Custom); in AVRTargetLowering()
98 setOperationAction(ISD::ROTL, MVT::i8, Custom); in AVRTargetLowering()
100 setOperationAction(ISD::ROTR, MVT::i8, Custom); in AVRTargetLowering()
103 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in AVRTargetLowering()
[all …]
H A DAVRCallingConv.td18 CCIfType<[i8], CCAssignToReg<[R24, R25]>>,
30 // i8 are always passed through the stack with a byte slot and byte alignment.
31 CCIfType<[i8], CCAssignToStack<1, 1>>,
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td68 def i8 : VTInt<8, 5>; // 8-bit integer value
102 def v1i8 : VTVec<1, i8, 34>; // 1 x i8 vector value
103 def v2i8 : VTVec<2, i8, 35>; // 2 x i8 vector value
104 def v3i8 : VTVec<3, i8, 36>; // 3 x i8 vector value
105 def v4i8 : VTVec<4, i8, 37>; // 4 x i8 vector value
106 def v8i8 : VTVec<8, i8, 38>; // 8 x i8 vector value
107 def v16i8 : VTVec<16, i8, 39>; // 16 x i8 vector value
108 def v32i8 : VTVec<32, i8, 40>; // 32 x i8 vector value
109 def v64i8 : VTVec<64, i8, 41>; // 64 x i8 vector value
110 def v128i8 : VTVec<128, i8, 42>; // 128 x i8 vector value
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrShiftRotate.td244 def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1 GR8:$src1)>;
245 def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1 GR16:$src1)>;
246 def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1 GR32:$src1)>;
247 def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1 GR64:$src1)>;
248 def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1 GR8:$src1)>;
249 def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1 GR16:$src1)>;
250 def : Pat<(rotr GR32:$src1, (i8 31)), (ROL32r1 GR32:$src1)>;
251 def : Pat<(rotr GR64:$src1, (i8 63)), (ROL64r1 GR64:$src1)>;
254 def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1_ND GR8:$src1)>;
255 def : Pat<(rotl GR16:$src1, (i8 1
[all...]
H A DX86InstrVecCompiler.td284 (i8 15)), (i8 15))>;
289 (i8 14)), (i8 14))>;
294 (i8 12)), (i8 12))>;
301 (i8 8)), (i8 8))>;
312 (i8 7)), (i8
[all...]
H A DX86InstrFragments.td16 [SDTCisVT<3, i8>, SDTCisVT<4, i8>, SDTCisVT<5, i32>]>;
21 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
25 SDTCisVT<2, i8>, SDTCisVT<3, i32>]>;
29 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
56 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 [SDTCisVT<0, i8>,
60 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
65 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
74 SDTCisVT<2, i8>]>;
[all …]
H A DX86CallingConv.td119 // Promote i1/i8/i16/v1i1 arguments to i32.
120 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
193 // Promote i1, v1i1, v8i1 arguments to i8.
194 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>,
203 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>,
244 // Scalar values are returned in AX first, then DX. For i8, the ABI
247 // the way LLVM does multiple return values -- a return of {i16,i8} would end
249 // for functions that return two i8 values are currently expected to pack the
254 CCIfType<[v1i1], CCPromoteToType<i8>>,
255 CCIfType<[i1], CCPromoteToType<i8>>,
[all …]
/freebsd/sys/i386/i386/
H A Dbpf_jit_machdep.h202 #define ADDib(i8, r32) do { \ argument
205 emitm(&stream, i8, 1); \
222 #define SUBib(i8, r32) do { \ argument
225 emitm(&stream, i8, 1); \
241 #define ANDib(i8, r8) do { \ argument
248 emitm(&stream, i8, 1); \
324 #define SHLib(i8, r32) do { \ argument
327 emitm(&stream, i8, 1); \
337 #define SHRib(i8, r32) do { \ argument
340 emitm(&stream, i8, 1); \
/freebsd/sys/amd64/amd64/
H A Dbpf_jit_machdep.h257 #define ADDib(i8, r32) do { \ argument
260 emitm(&stream, i8, 1); \
277 #define SUBib(i8, r64) do { \ argument
280 emitm(&stream, i8, 1); \
296 #define ANDib(i8, r8) do { \ argument
303 emitm(&stream, i8, 1); \
379 #define SHLib(i8, r32) do { \ argument
382 emitm(&stream, i8, 1); \
392 #define SHRib(i8, r32) do { \ argument
395 emitm(&stream, i8, 1); \
/freebsd/contrib/libarchive/libarchive/test/
H A Dtest_write_format_zip_file_zip64.c70 static unsigned i8(const unsigned char *p) { return (i4(p)); }
206 assertEqualInt(i8(p + 4), 44); /* We're using v1 Zip64 eocd */ in DEFINE_TEST()
211 assertEqualInt(i8(p + 24), 1); /* 1 entry on this disk */ in DEFINE_TEST()
212 assertEqualInt(i8(p + 32), 1); /* 1 entry total */ in DEFINE_TEST()
213 assertEqualInt(i8(p + 40), eocd - central_header); /* size of cd */ in DEFINE_TEST()
214 assertEqualInt(i8(p + 48), central_header - buff); /* start of cd */ in DEFINE_TEST()
215 p += 12 + i8(p + 4); in DEFINE_TEST()
219 assertEqualInt(i8(p + 8), eocd - buff); /* Offset of Zip64 eocd */ in DEFINE_TEST()
281 assertEqualInt(i8(p + 8), p - extension_end); /* compressed size */ in DEFINE_TEST()
282 assertEqualInt(i8( in DEFINE_TEST()
71 static unsigned i8(const unsigned char *p) { return (i4(p)); } i8() function
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA55.td389 def : InstRW<[CortexA55WriteAluVd_3], (instregex "[SU]ABDv(2i32|4i16|8i8)")>;
390 def : InstRW<[CortexA55WriteAluVq_3], (instregex "[SU]ABDv(16i8|4i32|8i16)")>;
396 def : InstRW<[CortexA55WriteAluVd_2], (instregex "(ADD|SUB|NEG)v(1i64|2i32|4i16|8i8)",
397 "[SU]R?HADDv(2i32|4i16|8i8)", "[SU]HSUBv(2i32|4i16|8i8)")>;
398 def : InstRW<[CortexA55WriteAluVq_2], (instregex "(ADD|SUB|NEG)v(2i64|4i32|8i16|16i8)",
399 "[SU]R?HADDv(8i16|4i32|16i8)", "[SU]HSUBv(8i16|4i32|16i8)")>;
401 def : InstRW<[CortexA55WriteAluVd_3], (instregex "ABSv(1i64|2i32|4i16|8i8)$",
403 "([SU]QADD|[SU]QSUB|SQNEG|SUQADD|USQADD)v(1i16|1i32|1i64|1i8|
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430CallingConv.td15 // i8 are returned in registers R12B, R13B, R14B, R15B
16 CCIfType<[i8], CCAssignToReg<[R12B, R13B, R14B, R15B]>>,
29 // Promote i8 arguments to i16.
30 CCIfType<[i8], CCPromoteToType<i16>>,
H A DMSP430ISelLowering.cpp49 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering()
61 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
68 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in MSP430TargetLowering()
73 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in MSP430TargetLowering()
75 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
76 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
77 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
81 setOperationAction(ISD::ROTL, MVT::i8, Expand); in MSP430TargetLowering()
82 setOperationAction(ISD::ROTR, MVT::i8, Expand); in MSP430TargetLowering()
89 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in MSP430TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiCallingConv.td19 // Promote i8/i16 args to i32
20 CCIfType<[i8, i16], CCPromoteToType<i32>>,
32 // Promote i8/i16 args to i32
33 CCIfType<[ i8, i16 ], CCPromoteToType<i32>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECallingConv.td31 // Promote i1/i8/i16/i32 arguments to i64.
32 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
62 // Promote i1/i8/i16/i32 arguments to i64.
63 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
79 // Promote i1/i8/i16/i32 return values to i64.
80 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMSA.txt72 bmz.v wd, ws, wt/i8 -> (vselect wt/i8, wd, ws)
73 bmnz.v wd, ws, wt/i8 -> (vselect wt/i8, ws, wd)
74 bsel.v wd, ws, wt/i8 -> (vselect wd, wt/i8, ws)
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.td44 CCIfType<[i8, i16], CCPromoteToType<i32>>,
56 CCIfType<[i8, i16], CCPromoteToType<i32>>,
66 CCIfType<[i8, i16], CCPromoteToType<i32>>,
78 CCIfType<[i8, i16], CCPromoteToType<i32>>,

12345678910