Lines Matching refs:i8

40   addRegisterClass(MVT::i8, &AVR::GPR8RegClass);  in AVRTargetLowering()
57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); in AVRTargetLowering()
65 setLoadExtAction(N, VT, MVT::i8, Expand); in AVRTargetLowering()
69 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in AVRTargetLowering()
85 setOperationAction(ISD::SRA, MVT::i8, Custom); in AVRTargetLowering()
86 setOperationAction(ISD::SHL, MVT::i8, Custom); in AVRTargetLowering()
87 setOperationAction(ISD::SRL, MVT::i8, Custom); in AVRTargetLowering()
98 setOperationAction(ISD::ROTL, MVT::i8, Custom); in AVRTargetLowering()
100 setOperationAction(ISD::ROTR, MVT::i8, Custom); in AVRTargetLowering()
103 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in AVRTargetLowering()
109 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in AVRTargetLowering()
113 setOperationAction(ISD::SETCC, MVT::i8, Custom); in AVRTargetLowering()
117 setOperationAction(ISD::SELECT, MVT::i8, Expand); in AVRTargetLowering()
123 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
125 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
127 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
129 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
151 setOperationAction(ISD::UDIV, MVT::i8, Expand); in AVRTargetLowering()
153 setOperationAction(ISD::UREM, MVT::i8, Expand); in AVRTargetLowering()
155 setOperationAction(ISD::SDIV, MVT::i8, Expand); in AVRTargetLowering()
157 setOperationAction(ISD::SREM, MVT::i8, Expand); in AVRTargetLowering()
161 setOperationAction(ISD::UDIVREM, MVT::i8, Custom); in AVRTargetLowering()
164 setOperationAction(ISD::SDIVREM, MVT::i8, Custom); in AVRTargetLowering()
169 setOperationAction(ISD::MUL, MVT::i8, Expand); in AVRTargetLowering()
179 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); in AVRTargetLowering()
180 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); in AVRTargetLowering()
261 return MVT::i8; in getSetCCResultType()
302 SDValue Cnt = DAG.getTargetConstant(ShiftAmount, dl, MVT::i8); in LowerShifts()
551 case MVT::i8: in LowerDivRem()
641 (LHS.getSimpleValueType() == MVT::i8)) && in getAVRCmp()
650 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, in getAVRCmp()
652 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, in getAVRCmp()
655 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8) in getAVRCmp()
656 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, in getAVRCmp()
659 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8) in getAVRCmp()
660 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, in getAVRCmp()
669 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8) in getAVRCmp()
670 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, in getAVRCmp()
673 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8) in getAVRCmp()
674 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, in getAVRCmp()
676 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, in getAVRCmp()
678 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, in getAVRCmp()
715 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8); in getAVRCmp()
756 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8); in getAVRCmp()
798 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi, in getAVRCmp()
836 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3, in getAVRCmp()
845 } else if (VT == MVT::i8 || VT == MVT::i16) { in getAVRCmp()
849 (VT == MVT::i8) in getAVRCmp()
851 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, in getAVRCmp()
862 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8); in getAVRCmp()
934 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8); in LowerINLINEASM()
1097 if (VT != MVT::i8 && VT != MVT::i16) { in getPreIndexedAddressParts()
1110 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) { in getPreIndexedAddressParts()
1115 Offset = DAG.getConstant(RHSC, DL, MVT::i8); in getPreIndexedAddressParts()
1154 if (VT != MVT::i8 && VT != MVT::i16) { in getPostIndexedAddressParts()
1166 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) { in getPostIndexedAddressParts()
1177 Offset = DAG.getConstant(RHSC, DL, MVT::i8); in getPostIndexedAddressParts()
1283 if (VT == MVT::i8) { in analyzeArguments()
1353 if (VT == MVT::i8) { in analyzeReturnValues()
1395 if (RegVT == MVT::i8) { in LowerFormalArguments()
1613 Ops.push_back(DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8)); in LowerCall()
1740 RetOps.push_back(DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8)); in LowerReturn()
2641 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
2647 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2651 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
2657 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
2663 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2669 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
2675 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
2680 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2685 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2690 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2695 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2768 if (Ty.getSimpleVT() == MVT::i8) { in LowerAsmOperandForConstraint()
2802 Result = DAG.getTargetConstant(0, DL, MVT::i8); in LowerAsmOperandForConstraint()