Lines Matching refs:i8
16 [SDTCisVT<3, i8>, SDTCisVT<4, i8>, SDTCisVT<5, i32>]>;
21 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
25 SDTCisVT<2, i8>, SDTCisVT<3, i32>]>;
29 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
56 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 [SDTCisVT<0, i8>,
60 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
65 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
74 SDTCisVT<2, i8>]>;
96 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
102 SDTCisVT<3, i8>,
137 SDTCisVT<4, i8>]>;
395 def X86_COND_O : PatLeaf<(i8 0)>;
396 def X86_COND_NO : PatLeaf<(i8 1)>;
397 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
398 def X86_COND_AE : PatLeaf<(i8 3)>; // alt. COND_NC
399 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
400 def X86_COND_NE : PatLeaf<(i8 5)>; // alt. COND_NZ
401 def X86_COND_BE : PatLeaf<(i8 6)>; // alt. COND_NA
402 def X86_COND_A : PatLeaf<(i8 7)>; // alt. COND_NBE
403 def X86_COND_S : PatLeaf<(i8 8)>;
404 def X86_COND_NS : PatLeaf<(i8 9)>;
405 def X86_COND_P : PatLeaf<(i8 10)>; // alt. COND_PE
406 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
407 def X86_COND_L : PatLeaf<(i8 12)>; // alt. COND_NGE
408 def X86_COND_GE : PatLeaf<(i8 13)>; // alt. COND_NL
409 def X86_COND_LE : PatLeaf<(i8 14)>; // alt. COND_NG
410 def X86_COND_G : PatLeaf<(i8 15)>; // alt. COND_NLE
455 def relocImm8_su : PatLeaf<(i8 relocImm), [{
498 // It's safe to fold a zextload/extload from i1 as a regular i8 load. The
501 def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{
509 // known to be 32-bit aligned or better. Ditto for i8 to i16.
553 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
564 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
574 // We can treat an i8/i16 extending load to i64 as a 32 bit load if its known