/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 891 switch (VT.getSimpleVT().SimpleTy) { in getLdStRegType() 951 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoad() 1077 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoadVector() 1127 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector() 1134 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_avar, in tryLoadVector() 1152 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector() 1159 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_asi, in tryLoadVector() 1179 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector() 1186 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_ari_64, in tryLoadVector() 1196 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector() [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.h | 95 return getSimpleVT().changeVectorElementTypeToInteger(); in changeVectorElementTypeToInteger() 105 return getSimpleVT().changeVectorElementType(EltVT.getSimpleVT()); in changeVectorElementType() 125 return getSimpleVT().changeTypeToInteger(); in changeTypeToInteger() 306 MVT getSimpleVT() const { in getSimpleVT() function
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H A D | TargetLowering.h | 1079 (unsigned)VT.getSimpleVT().SimpleTy < std::size(RegClassForVT)); in isTypeLegal() 1080 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr; in isTypeLegal() 1261 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; in getOperationAction() 1442 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getLoadExtAction() 1443 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction() 1466 unsigned ValI = (unsigned)ValVT.getSimpleVT().SimpleTy; in getAtomicLoadExtAction() 1467 unsigned MemI = (unsigned)MemVT.getSimpleVT().SimpleTy; in getAtomicLoadExtAction() 1489 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getTruncStoreAction() 1490 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getTruncStoreAction() 1528 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || in isIndexedLoadLegal() [all …]
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H A D | TargetCallingConv.h | 215 VT = vt.getSimpleVT(); in InputArg()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 247 MVT VT = RealVT.getSimpleVT(); in getRegForValue() 251 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); in getRegForValue() 310 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant() 392 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); in getRegForGEPIndex() 395 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); in getRegForGEPIndex() 475 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, CI->getZExtValue(), in selectBinaryOp() 476 VT.getSimpleVT()); in selectBinaryOp() 507 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm, in selectBinaryOp() 508 VT.getSimpleVT()); in selectBinaryOp() 522 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VVPISelLowering.cpp | 61 auto Packing = getTypePacking(LegalVecVT.getSimpleVT()); in lowerToVVP() 153 Packing, DataVT.getVectorElementType().getSimpleVT()); in lowerVVP_LOAD_STORE() 187 MVT DataVT = getIdiomaticVectorType(Op.getNode())->getSimpleVT(); in splitPackedLoadStore() 274 getLegalVectorType(Packing, DataVT.getVectorElementType().getSimpleVT()); in lowerVVP_GATHER_SCATTER() 320 MVT DataVT = getIdiomaticVectorType(Op.getNode())->getSimpleVT(); in legalizeInternalLoadStoreOp() 416 MVT IdiomVT = getIdiomaticVectorType(Op.getNode())->getSimpleVT(); in legalizePackedAVL()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 537 LoadConversionTbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost() 560 DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost() 572 DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost() 589 SrcTy.getSimpleVT(), DstTy.getSimpleVT())) in getCastInstrCost() 600 SrcTy.getSimpleVT(), DstTy.getSimpleVT())) in getCastInstrCost() 626 DstTy.getSimpleVT(), in getCastInstrCost() 627 SrcTy.getSimpleVT())) { in getCastInstrCost() 737 DstTy.getSimpleVT(), in getCastInstrCost() 738 SrcTy.getSimpleVT())) in getCastInstrCost() 767 DstTy.getSimpleVT(), in getCastInstrCost() [all …]
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H A D | ARMFastISel.cpp | 629 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() 676 VT = evt.getSimpleVT(); in isTypeLegal() 1342 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() 1537 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() 1779 MVT VT = FPVT.getSimpleVT(); in SelectBinaryFPOp() 2127 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet() 2192 return ARMMaterializeGV(GV, LCREVT.getSimpleVT()); in getLibcallReg() 2762 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt() 2763 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt() 3047 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 315 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad() 338 MVT VT = LD->getMemoryVT().getSimpleVT(); in tryIndexedLoad() 367 MVT VT = LD->getMemoryVT().getSimpleVT(); in tryIndexedBinOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
H A D | SPIRVISelLowering.h | 74 return ConditionVT.getSimpleVT(); in getPreferredSwitchConditionType()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 91 switch (LoadedVT.getSimpleVT().SimpleTy) { in INITIALIZE_PASS() 487 switch (StoredVT.getSimpleVT().SimpleTy) { in SelectIndexedStore() 708 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectExtractSubvector() 711 [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); in SelectExtractSubvector() 800 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectVAlign() 863 MVT OpTy = Op.getValueType().getSimpleVT(); in SelectTypecast() 870 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectP2D() 878 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectD2P() 887 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectV2Q() 889 MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy; in SelectV2Q() [all …]
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H A D | HexagonISelLowering.h | 421 return Op.getValueType().getSimpleVT(); in ty() 424 return { Ops.first.getValueType().getSimpleVT(), in ty() 425 Ops.second.getValueType().getSimpleVT() }; in ty()
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H A D | HexagonSubtarget.cpp | 188 MVT ElemTy = VecTy.getSimpleVT().getVectorElementType(); in isHVXVectorType() 234 MVT ElemTy = Ty.getVectorElementType().getSimpleVT(); in isTypeForHVX()
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H A D | HexagonISelDAGToDAGHVX.cpp | 678 : InpNode(Inp), InpTy(Inp->getValueType(0).getSimpleVT()) {} in ResultStack() 1189 MVT OpTy = Op.getValueType().getSimpleVT(); in materialize() 1871 MVT LegalTy = Lower.getTypeToTransformTo(Ctx, ElemTy).getSimpleVT(); in scalarizeShuffle() 2575 MVT ResTy = N->getValueType(0).getSimpleVT(); in selectExtractSubvector() 2578 [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); in selectExtractSubvector() 2595 MVT ResTy = N->getValueType(0).getSimpleVT(); in selectShuffle() 2676 MVT Ty = N->getValueType(0).getSimpleVT();
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H A D | HexagonISelLowering.cpp | 640 Subtarget.isHVXVectorType(VT.getSimpleVT()); in getPostIndexedAddressParts() 2166 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32; in isTruncateFree() 2186 MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT(); in isExtractSubvectorCheap() 3106 MVT MemTy = LN->getMemoryVT().getSimpleVT(); in LowerLoad() 3162 MVT StoreTy = SN->getMemoryVT().getSimpleVT(); in LowerStore() 3801 MVT SVT = VT.getSimpleVT(); in allowsMemoryAccess() 3813 MVT SVT = VT.getSimpleVT(); in allowsMisalignedMemoryAccesses()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelDAGToDAG.cpp | 123 MVT VT = cast<MemSDNode>(Op)->getMemoryVT().getSimpleVT(); in SelectAddr() 145 MVT VT = LD->getMemoryVT().getSimpleVT(); in selectIndexedLoad() 386 MVT VT = LD->getMemoryVT().getSimpleVT(); in select()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 448 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() 596 VT = evt.getSimpleVT(); in isTypeLegal() 1365 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments() 1734 MVT RVVT = RVEVT.getSimpleVT(); in selectRet() 1813 MVT SrcVT = SrcEVT.getSimpleVT(); in selectIntExt() 1814 MVT DestVT = DestEVT.getSimpleVT(); in selectIntExt() 1914 MVT DestVT = DestEVT.getSimpleVT(); in selectDivRem() 1975 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT(); in selectShift() 2091 MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT(); in getRegEnsuringSimpleIntegerWidening()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 296 VT = evt.getSimpleVT(); in isTypeLegal() 491 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore() 663 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore() 702 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend() 905 MVT PtrVT = TLI.getValueType(DL, U->getType()).getSimpleVT(); in X86SelectAddress() 1265 fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet() 1364 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode() 1386 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode() 1581 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt() 1625 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::SIGN_EXTEND, in X86SelectSExt() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | InlineAsmLowering.cpp | 267 TLI->getAsmOperandValueType(DL, OpTy, true).getSimpleVT(); in lowerInlineAsm() 277 TLI->getAsmOperandValueType(DL, Call.getType()).getSimpleVT(); in lowerInlineAsm()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 274 VT = Evt.getSimpleVT(); in isTypeLegal() 824 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp() 1076 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() 1751 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet() 1915 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt() 1916 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt() 2255 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 927 MVT SVT = VT.getSimpleVT(); in getTypeConversion() 1016 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in getTypeConversion() 1039 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in getTypeConversion() 1534 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown() 2206 MVT LoadMVT = LoadVT.getSimpleVT(); in isLoadBitCastBeneficial() 2211 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()) in isLoadBitCastBeneficial()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 232 MVT MT1 = VT1.getSimpleVT().SimpleTy; in isZExtFree() 233 MVT MT2 = VT2.getSimpleVT().SimpleTy; in isZExtFree() 352 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFrameLowering.cpp | 82 FuncInfo->addLocal(ValueVT.getSimpleVT()); in getLocalForStackObject()
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H A D | WebAssemblyFastISel.cpp | 121 return VT.isSimple() ? VT.getSimpleVT().SimpleTy in getSimpleType() 1178 Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(), in selectBitCast()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 544 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() 995 VT = evt.getSimpleVT(); in isTypeLegal() 1472 MVT VT = EVT.getSimpleVT(); in emitCmp() 2879 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP() 2938 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments() 3910 MVT RVVT = RVEVT.getSimpleVT(); in selectRet() 3961 MVT SrcVT = SrcEVT.getSimpleVT(); in selectTrunc() 3962 MVT DestVT = DestEVT.getSimpleVT(); in selectTrunc() 4618 MVT DestVT = DestEVT.getSimpleVT(); in selectRem() 4967 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*isZExt=*/false); in getRegForGEPIndex()
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