181ad6265SDimitry Andric //===-- SPIRVISelLowering.h - SPIR-V DAG Lowering Interface -----*- C++ -*-===// 281ad6265SDimitry Andric // 381ad6265SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 481ad6265SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 581ad6265SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 681ad6265SDimitry Andric // 781ad6265SDimitry Andric //===----------------------------------------------------------------------===// 881ad6265SDimitry Andric // 981ad6265SDimitry Andric // This file defines the interfaces that SPIR-V uses to lower LLVM code into a 1081ad6265SDimitry Andric // selection DAG. 1181ad6265SDimitry Andric // 1281ad6265SDimitry Andric //===----------------------------------------------------------------------===// 1381ad6265SDimitry Andric 1481ad6265SDimitry Andric #ifndef LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H 1581ad6265SDimitry Andric #define LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H 1681ad6265SDimitry Andric 17*0fca6ea1SDimitry Andric #include "SPIRVGlobalRegistry.h" 1881ad6265SDimitry Andric #include "llvm/CodeGen/TargetLowering.h" 19*0fca6ea1SDimitry Andric #include <set> 2081ad6265SDimitry Andric 2181ad6265SDimitry Andric namespace llvm { 2281ad6265SDimitry Andric class SPIRVSubtarget; 2381ad6265SDimitry Andric 2481ad6265SDimitry Andric class SPIRVTargetLowering : public TargetLowering { 25*0fca6ea1SDimitry Andric const SPIRVSubtarget &STI; 26*0fca6ea1SDimitry Andric 27*0fca6ea1SDimitry Andric // Record of already processed machine functions 28*0fca6ea1SDimitry Andric mutable std::set<const MachineFunction *> ProcessedMF; 29*0fca6ea1SDimitry Andric 3081ad6265SDimitry Andric public: SPIRVTargetLowering(const TargetMachine & TM,const SPIRVSubtarget & ST)3181ad6265SDimitry Andric explicit SPIRVTargetLowering(const TargetMachine &TM, 32*0fca6ea1SDimitry Andric const SPIRVSubtarget &ST) 33*0fca6ea1SDimitry Andric : TargetLowering(TM), STI(ST) {} 3481ad6265SDimitry Andric 3581ad6265SDimitry Andric // Stop IRTranslator breaking up FMA instrs to preserve types information. isFMAFasterThanFMulAndFAdd(const MachineFunction & MF,EVT)3681ad6265SDimitry Andric bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 3781ad6265SDimitry Andric EVT) const override { 3881ad6265SDimitry Andric return true; 3981ad6265SDimitry Andric } 4081ad6265SDimitry Andric 41*0fca6ea1SDimitry Andric // prevent creation of jump tables areJTsAllowed(const Function *)42*0fca6ea1SDimitry Andric bool areJTsAllowed(const Function *) const override { return false; } 43*0fca6ea1SDimitry Andric 4481ad6265SDimitry Andric // This is to prevent sexts of non-i64 vector indices which are generated 4581ad6265SDimitry Andric // within general IRTranslator hence type generation for it is omitted. getVectorIdxTy(const DataLayout & DL)4681ad6265SDimitry Andric MVT getVectorIdxTy(const DataLayout &DL) const override { 4781ad6265SDimitry Andric return MVT::getIntegerVT(32); 4881ad6265SDimitry Andric } 4981ad6265SDimitry Andric unsigned getNumRegistersForCallingConv(LLVMContext &Context, 5081ad6265SDimitry Andric CallingConv::ID CC, 5181ad6265SDimitry Andric EVT VT) const override; 5281ad6265SDimitry Andric MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 5381ad6265SDimitry Andric EVT VT) const override; 54bdd1243dSDimitry Andric bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 55bdd1243dSDimitry Andric MachineFunction &MF, 56bdd1243dSDimitry Andric unsigned Intrinsic) const override; 57*0fca6ea1SDimitry Andric 58*0fca6ea1SDimitry Andric std::pair<unsigned, const TargetRegisterClass *> 59*0fca6ea1SDimitry Andric getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 60*0fca6ea1SDimitry Andric StringRef Constraint, MVT VT) const override; 61*0fca6ea1SDimitry Andric unsigned 62*0fca6ea1SDimitry Andric getNumRegisters(LLVMContext &Context, EVT VT, 63*0fca6ea1SDimitry Andric std::optional<MVT> RegisterVT = std::nullopt) const override { 64*0fca6ea1SDimitry Andric return 1; 65*0fca6ea1SDimitry Andric } 66*0fca6ea1SDimitry Andric 67*0fca6ea1SDimitry Andric // Call the default implementation and finalize target lowering by inserting 68*0fca6ea1SDimitry Andric // extra instructions required to preserve validity of SPIR-V code imposed by 69*0fca6ea1SDimitry Andric // the standard. 70*0fca6ea1SDimitry Andric void finalizeLowering(MachineFunction &MF) const override; 71*0fca6ea1SDimitry Andric getPreferredSwitchConditionType(LLVMContext & Context,EVT ConditionVT)72*0fca6ea1SDimitry Andric MVT getPreferredSwitchConditionType(LLVMContext &Context, 73*0fca6ea1SDimitry Andric EVT ConditionVT) const override { 74*0fca6ea1SDimitry Andric return ConditionVT.getSimpleVT(); 75*0fca6ea1SDimitry Andric } 7681ad6265SDimitry Andric }; 7781ad6265SDimitry Andric } // namespace llvm 7881ad6265SDimitry Andric 7981ad6265SDimitry Andric #endif // LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H 80