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Searched refs:getOperand (Results 1 – 25 of 1115) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp241 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
264 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
302 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
306 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
307 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
311 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
312 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
317 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
321 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
322 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp33 const MCOperand &MO = MI.getOperand(Idx); in getOImmOpValue()
42 const MCOperand &MO = MI.getOperand(Idx); in getImmOpValueIDLY()
53 const MCOperand &MSB = MI.getOperand(Idx); in getImmOpValueMSBSize()
54 const MCOperand &LSB = MI.getOperand(Idx + 1); in getImmOpValueMSBSize()
78 .addOperand(MI.getOperand(0)) in expandJBTF()
85 .addOperand(MI.getOperand(1)) in expandJBTF()
86 .addOperand(MI.getOperand(2)); in expandJBTF()
88 TmpInst = MCInstBuilder(CSKY::JMPI32).addOperand(MI.getOperand(2)); in expandJBTF()
103 .addOperand(MI.getOperand(0)) in expandNEG()
104 .addOperand(MI.getOperand( in expandNEG()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp236 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
239 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
240 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
245 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
246 return 32 + MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
249 uint16_t Imm = MI->getOperand(2).getImm(); in getKnownLeadingZeroCount()
279 getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI), in getKnownLeadingZeroCount()
280 getKnownLeadingZeroCount(MI->getOperand(2).getReg(), TII, MRI)); in getKnownLeadingZeroCount()
287 getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI), in getKnownLeadingZeroCount()
288 getKnownLeadingZeroCount(MI->getOperand(2).getReg(), TII, MRI)); in getKnownLeadingZeroCount()
[all …]
H A DPPCVSXFMAMutate.cpp112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
130 Register AddendSrcReg = AddendMI->getOperand(1).getReg(); in processBlock()
132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
164 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { in processBlock()
186 Register OldFMAReg = MI.getOperand(0).getReg(); in processBlock()
190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock()
191 Register Reg3 = MI.getOperand(3).getReg(); in processBlock()
218 Register KilledProdReg = MI.getOperand(KilledProdOp).getReg(); in processBlock()
219 Register OtherProdReg = MI.getOperand(OtherProdOp).getReg(); in processBlock()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp154 Register DstReg = MI.getOperand(0).getReg(); in expandArith()
155 Register SrcReg = MI.getOperand(2).getReg(); in expandArith()
156 bool DstIsDead = MI.getOperand(0).isDead(); in expandArith()
157 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
158 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
159 bool ImpIsDead = MI.getOperand(3).isDead(); in expandArith()
175 MIBHI->getOperand(3).setIsDead(); in expandArith()
178 MIBHI->getOperand(4).setIsKill(); in expandArith()
187 Register DstReg = MI.getOperand(0).getReg(); in expandLogic()
188 Register SrcReg = MI.getOperand(2).getReg(); in expandLogic()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp49 const MCOperand &MO = MI->getOperand(OpNum); in printOperand()
78 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
79 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
84 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
85 MI->getOperand(OpNum + 1).getImm() == 0 && in printMemASXOperand()
86 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
87 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
88 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
95 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
96 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASXOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp79 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
86 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
103 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
128 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
129 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
130 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
131 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
132 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
133 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
144 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetStreamer.h33 A.getNumOperands() == 5 && A.getOperand(2).getImm() == 1 && in operator()
34 B.getOperand(2).getImm() == 1 && "Unexpected EXRL target MCInst"); in operator()
37 if (A.getOperand(0).getReg() != B.getOperand(0).getReg()) in operator()
38 return A.getOperand(0).getReg() < B.getOperand(0).getReg(); in operator()
39 if (A.getOperand(1).getImm() != B.getOperand(1).getImm()) in operator()
40 return A.getOperand(1).getImm() < B.getOperand( in operator()
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H A DSystemZAsmPrinter.cpp43 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
44 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
47 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
49 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
57 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
58 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
61 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
62 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
63 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp95 const MCOperand &Reg = MI->getOperand(0); in printInst()
103 const MCOperand &Reg = MI->getOperand(0); in printInst()
111 const MCOperand &Reg = MI->getOperand(0); in printInst()
119 const MCOperand &Reg = MI->getOperand(0); in printInst()
129 const MCOperand &Dst = MI->getOperand(0); in printInst()
130 const MCOperand &MO1 = MI->getOperand(1); in printInst()
131 const MCOperand &MO2 = MI->getOperand(2); in printInst()
132 const MCOperand &MO3 = MI->getOperand(3); in printInst()
152 const MCOperand &Dst = MI->getOperand(0); in printInst()
153 const MCOperand &MO1 = MI->getOperand(1); in printInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaInstPrinter.cpp83 printOperand(MI->getOperand(OpNum), O); in printOperand()
88 OS << getRegisterName(MI->getOperand(OpNum).getReg()); in printMemOperand()
95 const MCOperand &MC = MI->getOperand(OpNum); in printBranchTarget()
96 if (MI->getOperand(OpNum).isImm()) { in printBranchTarget()
110 const MCOperand &MC = MI->getOperand(OpNum); in printJumpTarget()
126 const MCOperand &MC = MI->getOperand(OpNum); in printCallOperand()
141 const MCOperand &MC = MI->getOperand(OpNum); in printL32RTarget()
143 int64_t Value = MI->getOperand(OpNum).getImm(); in printL32RTarget()
159 if (MI->getOperand(OpNum).isImm()) { in printImm8_AsmOperand()
160 int64_t Value = MI->getOperand(OpNum).getImm(); in printImm8_AsmOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp97 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
98 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
99 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
111 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
112 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
123 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
124 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
133 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
142 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
143 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
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H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp61 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
63 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
69 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
94 unsigned RegOp0 = Inst.getOperand(0).getReg(); in LowerCompactBranch()
95 unsigned RegOp1 = Inst.getOperand(1).getReg(); in LowerCompactBranch()
115 Inst.getOperand(0).setReg(RegOp1); in LowerCompactBranch()
116 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
228 const MCOperand &MO = MI.getOperand(OpNo); in encodeInstruction()
250 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue()
272 const MCOperand &MO = MI.getOperand(OpN in getBranchTargetOpValue1SImm16()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp43 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth); in computeKnownAlignment()
46 return Align(MI->getOperand(2).getImm()); in computeKnownAlignment()
49 int FrameIdx = MI->getOperand(1).getIndex(); in computeKnownAlignment()
64 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
199 computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
219 assert(MI.getOperand(0).getSubReg() == 0 && "Is this code in SSA?"); in computeKnownBitsImpl()
233 const MachineOperand &Src = MI.getOperand(Idx); in computeKnownBitsImpl()
261 Known = KnownBits::makeConstant(MI.getOperand(1).getCImm()->getValue()); in computeKnownBitsImpl()
265 int FrameIdx = MI.getOperand(1).getIndex(); in computeKnownBitsImpl()
270 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp112 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
113 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
143 OutOps.push_back(Op.getOperand(0)); in SelectInlineAsmMemoryOperand()
178 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
179 N->getOperand(2) }; in Select()
185 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
186 N->getOperand(2) }; in Select()
192 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
193 N->getOperand(2), N->getOperand(3) }; in Select()
199 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp103 MI->getOperand(1).getReg().isVirtual()) in INITIALIZE_PASS_DEPENDENCY()
104 MI = MRI->getVRegDef(MI->getOperand(1).getReg()); in INITIALIZE_PASS_DEPENDENCY()
124 if (T.getOpcode() == ARM::t2LoopEnd && T.getOperand(1).getMBB() == Header) { in findLoopComponents()
129 T.getOperand(2).getMBB() == Header) { in findLoopComponents()
153 LookThroughCOPY(MRI->getVRegDef(LoopEnd->getOperand(0).getReg()), MRI); in findLoopComponents()
162 LookThroughCOPY(MRI->getVRegDef(LoopDec->getOperand(1).getReg()), MRI); in findLoopComponents()
165 (LoopPhi->getOperand(2).getMBB() != Latch && in findLoopComponents()
166 LoopPhi->getOperand(4).getMBB() != Latch)) { in findLoopComponents()
172 Register StartReg = LoopPhi->getOperand(2).getMBB() == Latch in findLoopComponents()
173 ? LoopPhi->getOperand(3).getReg() in findLoopComponents()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp230 if (MI.getOperand(3).getImm() != 0) in visitORR()
233 if (MI.getOperand(1).getReg() != AArch64::WZR) in visitORR()
236 MachineInstr *SrcMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg()); in visitORR()
251 SrcMI->getOperand(1).getReg().isVirtual()) { in visitORR()
253 MRI->getRegClass(SrcMI->getOperand(1).getReg()); in visitORR()
259 SrcMI->getOperand(1).getSubReg() != AArch64::ssub)) in visitORR()
261 Register CpySrc = SrcMI->getOperand(1).getReg(); in visitORR()
262 if (SrcMI->getOperand(1).getSubReg() == AArch64::ssub) { in visitORR()
266 .add(SrcMI->getOperand(1)); in visitORR()
269 TII->get(AArch64::FMOVSWr), SrcMI->getOperand(0).getReg()) in visitORR()
[all …]
H A DAArch64ExpandPseudoInsts.cpp129 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
131 MI.getOperand(0).isRenamable() ? RegState::Renamable : 0; in expandMOVImm()
132 uint64_t Imm = MI.getOperand(1).getImm(); in expandMOVImm()
156 .add(MI.getOperand(0)) in expandMOVImm()
160 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
161 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
173 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
174 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
188 .add(MI.getOperand(0)) in expandMOVImm()
192 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
77 << getRegisterName(MI->getOperand(1).getReg()) << "], %" in printMemoryLoadIncrement()
78 << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
83 << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI) in printMemoryLoadIncrement()
84 << "], %" << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp91 const MachineOperand &HiOp1 = Hi.getOperand(1); in INITIALIZE_PASS()
106 Register HiDestReg = Hi.getOperand(0).getReg(); in INITIALIZE_PASS()
115 const MachineOperand &LoOp2 = Lo->getOperand(2); in INITIALIZE_PASS()
149 Hi.getOperand(1).setOffset(Offset); in foldOffset()
151 Lo.getOperand(2).setOffset(Offset); in foldOffset()
153 MRI->constrainRegClass(Lo.getOperand(0).getReg(), in foldOffset()
154 MRI->getRegClass(Tail.getOperand(0).getReg())); in foldOffset()
155 MRI->replaceRegWith(Tail.getOperand(0).getReg(), Lo.getOperand(0).getReg()); in foldOffset()
186 Register Rs = TailAdd.getOperand(1).getReg(); in foldLargeOffset()
187 Register Rt = TailAdd.getOperand(2).getReg(); in foldLargeOffset()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp107 Register DstReg = I.getOperand(0).getReg(); in selectCopy()
184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode()
263 .add(I.getOperand(0)) in buildUnalignedStore()
301 isRegInGprb(I.getOperand(0).getReg(), MRI)) { in select()
303 .add(I.getOperand(0)) in select()
304 .add(I.getOperand(1)) in select()
305 .add(I.getOperand(2)); in select()
308 Mul->getOperand(3).setIsDead(true); in select()
309 Mul->getOperand(4).setIsDead(true); in select()
328 .add(I.getOperand(1)) in select()
[all …]
H A DMipsSEISelLowering.cpp416 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
417 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
418 Op->getOperand(2)); in lowerSELECT()
487 SDValue Op0 = N->getOperand(0); in performANDCombine()
488 SDValue Op1 = N->getOperand(1); in performANDCombine()
507 SDValue Op0Op2 = Op0->getOperand(2); in performANDCombine()
514 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; in performANDCombine()
557 N = N->getOperand(0); in isVectorAllOnes()
581 if (isVectorAllOnes(N->getOperand(0))) in isBitwiseInverse()
582 return N->getOperand(1) == OfNode; in isBitwiseInverse()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp160 ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask(); in matchREV()
161 Register Dst = MI.getOperand(0).getReg(); in matchREV()
162 Register Src = MI.getOperand(1).getReg(); in matchREV()
197 ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask(); in matchTRN()
198 Register Dst = MI.getOperand(0).getReg(); in matchTRN()
203 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
204 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
218 ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask(); in matchUZP()
219 Register Dst = MI.getOperand(0).getReg(); in matchUZP()
224 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp162 auto Op = MI.getOperand(1); in isAsCheapAsAMove()
225 if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB) in findLoopInstr()
305 const MachineOperand OpFI = MI.getOperand(1); in isLoadFromStackSlot()
308 const MachineOperand OpOff = MI.getOperand(2); in isLoadFromStackSlot()
312 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
319 const MachineOperand OpFI = MI.getOperand(2); in isLoadFromStackSlot()
322 const MachineOperand OpOff = MI.getOperand(3); in isLoadFromStackSlot()
326 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
353 const MachineOperand &OpFI = MI.getOperand(0); in isStoreToStackSlot()
356 const MachineOperand &OpOff = MI.getOperand(1); in isStoreToStackSlot()
[all …]

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