Home
last modified time | relevance | path

Searched refs:getOperand (Results 1 – 25 of 1184) sorted by relevance

12345678910>>...48

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp272 MCRegister OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
295 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
333 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
337 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
338 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
342 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
343 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
348 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
352 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
353 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp104 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
122 Register AddendSrcReg = AddendMI->getOperand(1).getReg(); in processBlock()
124 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
130 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
156 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { in processBlock()
178 Register OldFMAReg = MI.getOperand(0).getReg(); in processBlock()
182 Register Reg2 = MI.getOperand(2).getReg(); in processBlock()
183 Register Reg3 = MI.getOperand(3).getReg(); in processBlock()
210 Register KilledProdReg = MI.getOperand(KilledProdOp).getReg(); in processBlock()
211 Register OtherProdReg = MI.getOperand(OtherProdOp).getReg(); in processBlock()
[all …]
H A DPPCMIPeephole.cpp232 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
235 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
236 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
241 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
242 return 32 + MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
245 uint16_t Imm = MI->getOperand(2).getImm(); in getKnownLeadingZeroCount()
275 getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI), in getKnownLeadingZeroCount()
276 getKnownLeadingZeroCount(MI->getOperand(2).getReg(), TII, MRI)); in getKnownLeadingZeroCount()
283 getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI), in getKnownLeadingZeroCount()
284 getKnownLeadingZeroCount(MI->getOperand(2).getReg(), TII, MRI)); in getKnownLeadingZeroCount()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp50 const MCOperand &MO = MI->getOperand(OpNum); in printOperand()
71 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
72 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
77 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
78 MI->getOperand(OpNum + 1).getImm() == 0 && in printMemASXOperand()
79 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
80 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
81 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
88 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
89 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASXOperand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp79 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
86 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
103 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
128 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
129 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
130 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
131 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
132 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
133 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
144 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp152 Register DstReg = MI.getOperand(0).getReg(); in expandArith()
153 Register SrcReg = MI.getOperand(2).getReg(); in expandArith()
154 bool DstIsDead = MI.getOperand(0).isDead(); in expandArith()
155 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
156 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
157 bool ImpIsDead = MI.getOperand(3).isDead(); in expandArith()
173 MIBHI->getOperand(3).setIsDead(); in expandArith()
176 MIBHI->getOperand(4).setIsKill(); in expandArith()
185 Register DstReg = MI.getOperand(0).getReg(); in expandLogic()
186 Register SrcReg = MI.getOperand(2).getReg(); in expandLogic()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaInstPrinter.cpp74 printOperand(MI->getOperand(OpNum), O); in printOperand()
79 OS << getRegisterName(MI->getOperand(OpNum).getReg()); in printMemOperand()
86 const MCOperand &MC = MI->getOperand(OpNum); in printBranchTarget()
87 if (MI->getOperand(OpNum).isImm()) { in printBranchTarget()
98 const MCOperand &MC = MI->getOperand(OpNum); in printLoopTarget()
99 if (MI->getOperand(OpNum).isImm()) { in printLoopTarget()
110 const MCOperand &MC = MI->getOperand(OpNum); in printJumpTarget()
123 const MCOperand &MC = MI->getOperand(OpNum); in printCallOperand()
145 const MCOperand &MC = MI->getOperand(OpNum); in printL32RTarget()
147 int64_t Value = MI->getOperand(OpNum).getImm(); in printL32RTarget()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp79 const MCOperand &MO = MI.getOperand(Idx); in getImmOpValue()
117 const MCOperand &MO = MI.getOperand(Idx); in getImmShiftOpValue()
128 const MCOperand &MO = MI.getOperand(Idx); in getBranchSymbolOpValue()
147 const MCOperand &MO = MI.getOperand(Idx); in getConstpoolSymbolOpValue()
162 const MCOperand &MO = MI.getOperand(Idx); in getDataSymbolOpValue()
176 const MCOperand &MO = MI.getOperand(Idx); in getCallSymbolOpValue()
190 const MCOperand &MO = MI.getOperand(Idx); in getBareSymbolOpValue()
216 const MCOperand &MO = MI.getOperand(Idx); in getOImmOpValue()
225 const MCOperand &MO = MI.getOperand(Idx); in getImmOpValueIDLY()
236 const MCOperand &MSB = MI.getOperand(Idx); in getImmOpValueMSBSize()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp91 User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm(); in hasSameEEW()
93 Src.getOperand(RISCVII::getSEWOpNum(Src.getDesc())).getImm(); in hasSameEEW()
151 MachineOperand &VL = MI.getOperand(RISCVII::getVLOpNum(MI.getDesc())); in tryToReduceVL()
157 Register SrcReg = MI.getOperand(SrcIdx).getReg(); in tryToReduceVL()
179 Src->getOperand(RISCVII::getVLOpNum(Src->getDesc())); in tryToReduceVL()
207 Def->getOperand(1).getReg() != RISCV::X0) in getConstant()
209 return Def->getOperand(2).getImm(); in getConstant()
221 unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm(); in convertToVLMAX()
228 MachineOperand &VL = MI.getOperand(RISCVII::getVLOpNum(MI.getDesc())); in convertToVLMAX()
247 assert(Def->getOperand(2).getImm() < 64); in convertToVLMAX()
[all …]
H A DRISCVFoldMemOffset.cpp116 if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg()); in foldOffset()
119 if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg()); in foldOffset()
124 if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg()); in foldOffset()
127 if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg()); in foldOffset()
132 if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg()); in foldOffset()
135 if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg()); in foldOffset()
140 if (auto I = RegToOffsetMap.find(User.getOperand(1).getReg()); in foldOffset()
143 if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg()); in foldOffset()
152 if (User.getOperand(1).getReg() == Reg) in foldOffset()
154 if (auto I = RegToOffsetMap.find(User.getOperand(2).getReg()); in foldOffset()
[all …]
H A DRISCVMergeBaseOffset.cpp90 const MachineOperand &HiOp1 = Hi.getOperand(1); in INITIALIZE_PASS()
105 Register HiDestReg = Hi.getOperand(0).getReg(); in INITIALIZE_PASS()
114 const MachineOperand &LoOp2 = Lo->getOperand(2); in INITIALIZE_PASS()
151 if (Hi.getOpcode() == RISCV::AUIPC && Hi.getOperand(1).isGlobal()) { in foldOffset()
152 const GlobalValue *GV = Hi.getOperand(1).getGlobal(); in foldOffset()
160 Hi.getOperand(1).setOffset(Offset); in foldOffset()
162 Lo.getOperand(2).setOffset(Offset); in foldOffset()
164 MRI->constrainRegClass(Lo.getOperand(0).getReg(), in foldOffset()
165 MRI->getRegClass(Tail.getOperand(0).getReg())); in foldOffset()
166 MRI->replaceRegWith(Tail.getOperand(0).getReg(), Lo.getOperand(0).getReg()); in foldOffset()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp93 const MCOperand &Reg = MI->getOperand(0); in printInst()
101 const MCOperand &Reg = MI->getOperand(0); in printInst()
109 const MCOperand &Reg = MI->getOperand(0); in printInst()
117 const MCOperand &Reg = MI->getOperand(0); in printInst()
127 const MCOperand &Dst = MI->getOperand(0); in printInst()
128 const MCOperand &MO1 = MI->getOperand(1); in printInst()
129 const MCOperand &MO2 = MI->getOperand(2); in printInst()
130 const MCOperand &MO3 = MI->getOperand(3); in printInst()
150 const MCOperand &Dst = MI->getOperand(0); in printInst()
151 const MCOperand &MO1 = MI->getOperand(1); in printInst()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchMergeBaseOffset.cpp108 const MachineOperand &Hi20Op1 = Hi20.getOperand(1); in INITIALIZE_PASS()
119 Register HiDestReg = Hi20.getOperand(0).getReg(); in INITIALIZE_PASS()
133 Register LastOp1Reg = Last->getOperand(1).getReg(); in INITIALIZE_PASS()
137 const MachineOperand &Hi12Op2 = Hi12->getOperand(2); in INITIALIZE_PASS()
142 if (!MRI->hasOneUse(Hi12->getOperand(0).getReg())) in INITIALIZE_PASS()
145 Lo20 = MRI->getVRegDef(Hi12->getOperand(1).getReg()); in INITIALIZE_PASS()
146 const MachineOperand &Lo20Op2 = Lo20->getOperand(2); in INITIALIZE_PASS()
151 if (!MRI->hasOneUse(Lo20->getOperand(0).getReg())) in INITIALIZE_PASS()
154 Lo12 = MRI->getVRegDef(Lo20->getOperand(1).getReg()); in INITIALIZE_PASS()
155 if (!MRI->hasOneUse(Lo12->getOperand(0).getReg())) in INITIALIZE_PASS()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp97 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
98 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
99 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
111 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
112 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
123 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
124 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
133 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
142 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
143 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
[all …]
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp236 if (MI.getOperand(3).getImm() != 0) in visitORR()
239 if (MI.getOperand(1).getReg() != AArch64::WZR) in visitORR()
242 MachineInstr *SrcMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg()); in visitORR()
257 SrcMI->getOperand(1).getReg().isVirtual()) { in visitORR()
259 MRI->getRegClass(SrcMI->getOperand(1).getReg()); in visitORR()
266 SrcMI->getOperand(1).getSubReg() != AArch64::ssub)) in visitORR()
269 if (SrcMI->getOperand(1).getSubReg() == AArch64::ssub) { in visitORR()
273 .add(SrcMI->getOperand(1)); in visitORR()
275 CpySrc = SrcMI->getOperand(1).getReg(); in visitORR()
278 TII->get(AArch64::FMOVSWr), SrcMI->getOperand(0).getReg()) in visitORR()
[all …]
H A DAArch64ExpandPseudoInsts.cpp129 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
131 MI.getOperand(0).isRenamable() ? RegState::Renamable : 0; in expandMOVImm()
132 uint64_t Imm = MI.getOperand(1).getImm(); in expandMOVImm()
156 .add(MI.getOperand(0)) in expandMOVImm()
160 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
161 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
173 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
174 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
188 .add(MI.getOperand(0)) in expandMOVImm()
192 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp86 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
88 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
94 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
119 MCRegister RegOp0 = Inst.getOperand(0).getReg(); in LowerCompactBranch()
120 MCRegister RegOp1 = Inst.getOperand(1).getReg(); in LowerCompactBranch()
140 Inst.getOperand(0).setReg(RegOp1); in LowerCompactBranch()
141 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
253 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue()
274 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue1SImm16()
295 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValueMMR6()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp46 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
48 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
49 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
53 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
58 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
63 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
74 << getRegisterName(MI->getOperand(1).getReg()) << "], %" in printMemoryLoadIncrement()
75 << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
80 << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI) in printMemoryLoadIncrement()
81 << "], %" << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp46 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
47 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
50 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
51 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
52 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
60 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
61 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
64 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
65 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
66 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZTargetStreamer.h38 A.getNumOperands() == 5 && A.getOperand(2).getImm() == 1 && in operator()
39 B.getOperand(2).getImm() == 1 && "Unexpected EXRL target MCInst"); in operator()
42 if (A.getOperand(0).getReg() != B.getOperand(0).getReg()) in operator()
43 return A.getOperand(0).getReg() < B.getOperand(0).getReg(); in operator()
44 if (A.getOperand(1).getImm() != B.getOperand(1).getImm()) in operator()
45 return A.getOperand(1).getImm() < B.getOperand(1).getImm(); in operator()
46 if (A.getOperand(3).getReg() != B.getOperand(3).getReg()) in operator()
47 return A.getOperand(3).getReg() < B.getOperand(3).getReg(); in operator()
48 if (A.getOperand(4).getImm() != B.getOperand(4).getImm()) in operator()
49 return A.getOperand(4).getImm() < B.getOperand(4).getImm(); in operator()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp102 MI->getOperand(1).getReg().isVirtual()) in INITIALIZE_PASS_DEPENDENCY()
103 MI = MRI->getVRegDef(MI->getOperand(1).getReg()); in INITIALIZE_PASS_DEPENDENCY()
123 if (T.getOpcode() == ARM::t2LoopEnd && T.getOperand(1).getMBB() == Header) { in findLoopComponents()
128 T.getOperand(2).getMBB() == Header) { in findLoopComponents()
152 LookThroughCOPY(MRI->getVRegDef(LoopEnd->getOperand(0).getReg()), MRI); in findLoopComponents()
161 LookThroughCOPY(MRI->getVRegDef(LoopDec->getOperand(1).getReg()), MRI); in findLoopComponents()
164 (LoopPhi->getOperand(2).getMBB() != Latch && in findLoopComponents()
165 LoopPhi->getOperand(4).getMBB() != Latch)) { in findLoopComponents()
171 Register StartReg = LoopPhi->getOperand(2).getMBB() == Latch in findLoopComponents()
172 ? LoopPhi->getOperand(3).getReg() in findLoopComponents()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp107 Register DstReg = I.getOperand(0).getReg(); in selectCopy()
184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode()
263 .add(I.getOperand(0)) in buildUnalignedStore()
301 isRegInGprb(I.getOperand(0).getReg(), MRI)) { in select()
303 .add(I.getOperand(0)) in select()
304 .add(I.getOperand(1)) in select()
305 .add(I.getOperand(2)); in select()
308 Mul->getOperand(3).setIsDead(true); in select()
309 Mul->getOperand(4).setIsDead(true); in select()
328 .add(I.getOperand(1)) in select()
[all …]
H A DMipsSEISelLowering.cpp455 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
456 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
457 Op->getOperand(2)); in lowerSELECT()
526 SDValue Op0 = N->getOperand(0); in performANDCombine()
527 SDValue Op1 = N->getOperand(1); in performANDCombine()
546 SDValue Op0Op2 = Op0->getOperand(2); in performANDCombine()
553 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; in performANDCombine()
596 N = N->getOperand(0); in isVectorAllOnes()
620 if (isVectorAllOnes(N->getOperand(0))) in isBitwiseInverse()
621 return N->getOperand(1) == OfNode; in isBitwiseInverse()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp160 auto Op = MI.getOperand(1); in isAsCheapAsAMove()
223 if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB) in findLoopInstr()
303 const MachineOperand OpFI = MI.getOperand(1); in isLoadFromStackSlot()
306 const MachineOperand OpOff = MI.getOperand(2); in isLoadFromStackSlot()
310 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
317 const MachineOperand OpFI = MI.getOperand(2); in isLoadFromStackSlot()
320 const MachineOperand OpOff = MI.getOperand(3); in isLoadFromStackSlot()
324 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
351 const MachineOperand &OpFI = MI.getOperand(0); in isStoreToStackSlot()
354 const MachineOperand &OpOff = MI.getOperand(1); in isStoreToStackSlot()
[all …]

12345678910>>...48