Lines Matching refs:getOperand
162 auto Op = MI.getOperand(1); in isAsCheapAsAMove()
225 if (Opc == EndLoopOp && I.getOperand(0).getMBB() != TargetBB) in findLoopInstr()
305 const MachineOperand OpFI = MI.getOperand(1); in isLoadFromStackSlot()
308 const MachineOperand OpOff = MI.getOperand(2); in isLoadFromStackSlot()
312 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
319 const MachineOperand OpFI = MI.getOperand(2); in isLoadFromStackSlot()
322 const MachineOperand OpOff = MI.getOperand(3); in isLoadFromStackSlot()
326 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
353 const MachineOperand &OpFI = MI.getOperand(0); in isStoreToStackSlot()
356 const MachineOperand &OpOff = MI.getOperand(1); in isStoreToStackSlot()
360 return MI.getOperand(2).getReg(); in isStoreToStackSlot()
371 const MachineOperand &OpFI = MI.getOperand(1); in isStoreToStackSlot()
374 const MachineOperand &OpOff = MI.getOperand(2); in isStoreToStackSlot()
378 return MI.getOperand(3).getReg(); in isStoreToStackSlot()
479 I->getOperand(0).isMBB(); in analyzeBranch()
482 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { in analyzeBranch()
514 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB()) in analyzeBranch()
517 !SecondLastInst->getOperand(0).isMBB()) in analyzeBranch()
523 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB()) in analyzeBranch()
529 TBB = LastInst->getOperand(0).getMBB(); in analyzeBranch()
533 TBB = LastInst->getOperand(0).getMBB(); in analyzeBranch()
535 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
539 TBB = LastInst->getOperand(1).getMBB(); in analyzeBranch()
541 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
546 TBB = LastInst->getOperand(2).getMBB(); in analyzeBranch()
548 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
549 Cond.push_back(LastInst->getOperand(1)); in analyzeBranch()
561 if (!SecondLastInst->getOperand(1).isMBB()) in analyzeBranch()
563 TBB = SecondLastInst->getOperand(1).getMBB(); in analyzeBranch()
565 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
566 FBB = LastInst->getOperand(0).getMBB(); in analyzeBranch()
574 TBB = SecondLastInst->getOperand(2).getMBB(); in analyzeBranch()
576 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
577 Cond.push_back(SecondLastInst->getOperand(1)); in analyzeBranch()
578 FBB = LastInst->getOperand(0).getMBB(); in analyzeBranch()
585 TBB = SecondLastInst->getOperand(0).getMBB(); in analyzeBranch()
594 TBB = SecondLastInst->getOperand(0).getMBB(); in analyzeBranch()
596 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
597 FBB = LastInst->getOperand(0).getMBB(); in analyzeBranch()
673 Loop->getOperand(0).setMBB(TBB); in insertBranch()
715 Loop->getOperand(0).setMBB(TBB); in insertBranch()
746 : Loop->getOperand(1).getImm(); in HexagonPipelinerLoopInfo()
748 LoopCount = Loop->getOperand(1).getReg(); in HexagonPipelinerLoopInfo()
767 Cond.push_back(NewCmp->getOperand(0)); in createTripCountGreaterCondition()
784 int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust; in adjustTripCount()
786 Loop->getOperand(1).setImm(TripCount); in adjustTripCount()
792 Register LoopCount = Loop->getOperand(1).getReg(); in adjustTripCount()
798 Loop->getOperand(1).setReg(NewLoopCount); in adjustTripCount()
813 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs); in analyzeLoopForPipelining()
1062 Register Mx = MI.getOperand(MxOp).getReg(); in expandPostRAPseudo()
1065 .add(MI.getOperand((HasImm ? 5 : 4))); in expandPostRAPseudo()
1066 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0)) in expandPostRAPseudo()
1067 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3)); in expandPostRAPseudo()
1069 MIB.add(MI.getOperand(4)); in expandPostRAPseudo()
1085 auto Op0 = MI.getOperand(0); in expandPostRAPseudo()
1093 MachineOperand &Op1 = MI.getOperand(1); in expandPostRAPseudo()
1122 MachineOperand &MD = MI.getOperand(0); in expandPostRAPseudo()
1123 MachineOperand &MS = MI.getOperand(1); in expandPostRAPseudo()
1133 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1135 .addImm(-MI.getOperand(1).getImm()); in expandPostRAPseudo()
1139 Register SrcReg = MI.getOperand(1).getReg(); in expandPostRAPseudo()
1140 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1146 unsigned Kill = getKillRegState(MI.getOperand(1).isKill()); in expandPostRAPseudo()
1154 Register SrcReg = MI.getOperand(1).getReg(); in expandPostRAPseudo()
1155 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1157 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill()); in expandPostRAPseudo()
1163 Register SrcReg = MI.getOperand(1).getReg(); in expandPostRAPseudo()
1164 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1166 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill()); in expandPostRAPseudo()
1172 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1173 const MachineOperand &BaseOp = MI.getOperand(1); in expandPostRAPseudo()
1175 int Offset = MI.getOperand(2).getImm(); in expandPostRAPseudo()
1187 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1188 const MachineOperand &BaseOp = MI.getOperand(1); in expandPostRAPseudo()
1190 int Offset = MI.getOperand(2).getImm(); in expandPostRAPseudo()
1209 const MachineOperand &SrcOp = MI.getOperand(2); in expandPostRAPseudo()
1211 const MachineOperand &BaseOp = MI.getOperand(0); in expandPostRAPseudo()
1213 int Offset = MI.getOperand(1).getImm(); in expandPostRAPseudo()
1226 Register SrcReg = MI.getOperand(2).getReg(); in expandPostRAPseudo()
1227 const MachineOperand &BaseOp = MI.getOperand(0); in expandPostRAPseudo()
1229 int Offset = MI.getOperand(1).getImm(); in expandPostRAPseudo()
1248 Register Reg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1256 Register Reg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1264 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1271 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1278 Register Vd = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1287 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1288 Register Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo()
1289 Register Src2Reg = MI.getOperand(2).getReg(); in expandPostRAPseudo()
1311 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo()
1312 Register Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo()
1313 Register Src2Reg = MI.getOperand(2).getReg(); in expandPostRAPseudo()
1314 Register Src3Reg = MI.getOperand(3).getReg(); in expandPostRAPseudo()
1341 const MachineOperand &Op0 = MI.getOperand(0); in expandPostRAPseudo()
1342 const MachineOperand &Op1 = MI.getOperand(1); in expandPostRAPseudo()
1343 const MachineOperand &Op2 = MI.getOperand(2); in expandPostRAPseudo()
1344 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo()
1365 const MachineOperand &Op0 = MI.getOperand(0); in expandPostRAPseudo()
1366 const MachineOperand &Op1 = MI.getOperand(1); in expandPostRAPseudo()
1367 const MachineOperand &Op2 = MI.getOperand(2); in expandPostRAPseudo()
1368 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo()
1398 MachineOperand &Op0 = MI.getOperand(0); in expandPostRAPseudo()
1399 MachineOperand &Op1 = MI.getOperand(1); in expandPostRAPseudo()
1400 MachineOperand &Op2 = MI.getOperand(2); in expandPostRAPseudo()
1401 MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo()
1555 .add(MI.getOperand(2)) in expandVGatherPseudo()
1556 .add(MI.getOperand(3)) in expandVGatherPseudo()
1557 .add(MI.getOperand(4)); in expandVGatherPseudo()
1559 .add(MI.getOperand(0)) in expandVGatherPseudo()
1560 .addImm(MI.getOperand(1).getImm()) in expandVGatherPseudo()
1567 .add(MI.getOperand(2)) in expandVGatherPseudo()
1568 .add(MI.getOperand(3)) in expandVGatherPseudo()
1569 .add(MI.getOperand(4)); in expandVGatherPseudo()
1571 .add(MI.getOperand(0)) in expandVGatherPseudo()
1572 .addImm(MI.getOperand(1).getImm()) in expandVGatherPseudo()
1579 .add(MI.getOperand(2)) in expandVGatherPseudo()
1580 .add(MI.getOperand(3)) in expandVGatherPseudo()
1581 .add(MI.getOperand(4)); in expandVGatherPseudo()
1583 .add(MI.getOperand(0)) in expandVGatherPseudo()
1584 .addImm(MI.getOperand(1).getImm()) in expandVGatherPseudo()
1591 .add(MI.getOperand(2)) in expandVGatherPseudo()
1592 .add(MI.getOperand(3)) in expandVGatherPseudo()
1593 .add(MI.getOperand(4)) in expandVGatherPseudo()
1594 .add(MI.getOperand(5)); in expandVGatherPseudo()
1596 .add(MI.getOperand(0)) in expandVGatherPseudo()
1597 .addImm(MI.getOperand(1).getImm()) in expandVGatherPseudo()
1604 .add(MI.getOperand(2)) in expandVGatherPseudo()
1605 .add(MI.getOperand(3)) in expandVGatherPseudo()
1606 .add(MI.getOperand(4)) in expandVGatherPseudo()
1607 .add(MI.getOperand(5)); in expandVGatherPseudo()
1609 .add(MI.getOperand(0)) in expandVGatherPseudo()
1610 .addImm(MI.getOperand(1).getImm()) in expandVGatherPseudo()
1617 .add(MI.getOperand(2)) in expandVGatherPseudo()
1618 .add(MI.getOperand(3)) in expandVGatherPseudo()
1619 .add(MI.getOperand(4)) in expandVGatherPseudo()
1620 .add(MI.getOperand(5)); in expandVGatherPseudo()
1622 .add(MI.getOperand(0)) in expandVGatherPseudo()
1623 .addImm(MI.getOperand(1).getImm()) in expandVGatherPseudo()
1694 MachineOperand &Op = MI.getOperand(NOp); in PredicateInstruction()
1708 T.add(MI.getOperand(NOp++)); in PredicateInstruction()
1714 MI.addOperand(T->getOperand(i)); in PredicateInstruction()
1902 SrcReg = MI.getOperand(1).getReg(); in analyzeCompare()
1911 SrcReg = MI.getOperand(1).getReg(); in analyzeCompare()
1920 SrcReg = MI.getOperand(1).getReg(); in analyzeCompare()
1942 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1959 const MachineOperand &Op2 = MI.getOperand(2); in analyzeCompare()
1962 Value = MI.getOperand(2).getImm(); in analyzeCompare()
2001 const MachineOperand &BaseA = MIa.getOperand(BasePosA); in areMemAccessesTriviallyDisjoint()
2009 const MachineOperand &BaseB = MIb.getOperand(BasePosB); in areMemAccessesTriviallyDisjoint()
2021 const MachineOperand &OffA = MIa.getOperand(OffsetPosA); in areMemAccessesTriviallyDisjoint()
2022 const MachineOperand &OffB = MIb.getOperand(OffsetPosB); in areMemAccessesTriviallyDisjoint()
2023 if (!MIa.getOperand(OffsetPosA).isImm() || in areMemAccessesTriviallyDisjoint()
2024 !MIb.getOperand(OffsetPosB).isImm()) in areMemAccessesTriviallyDisjoint()
2050 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos); in getIncrementValue()
2056 const MachineOperand &AddOp = MI.getOperand(2); in getIncrementValue()
2161 const MachineOperand &MO = MI.getOperand(ExtOpNum); in isConstExtended()
2691 Register DstReg = MI1.getOperand(0).getReg(); in isToBeScheduledASAP()
2694 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg()) in isToBeScheduledASAP()
2699 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2700 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
3088 const MachineOperand &Op = Second.getOperand(0); in canExecuteInBundle()
3098 Second.getOperand(Second.getNumOperands() - 1); in canExecuteInBundle()
3102 const MachineOperand &Op = First.getOperand(i); in canExecuteInBundle()
3310 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos); in getBaseAndOffset()
3316 const MachineOperand &BaseOp = MI.getOperand(BasePos); in getBaseAndOffset()
3350 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm()) in getBaseAndOffsetPosition()
3441 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3442 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3443 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
3453 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3454 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3457 isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() && in getCompoundCandidateGroup()
3458 ((isUInt<5>(MI.getOperand(2).getImm())) || in getCompoundCandidateGroup()
3459 (MI.getOperand(2).getImm() == -1))) in getCompoundCandidateGroup()
3464 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3465 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3473 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3478 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3479 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3482 MI.getOperand(2).isImm() && in getCompoundCandidateGroup()
3483 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0)) in getCompoundCandidateGroup()
3494 Src1Reg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
3520 Register DestReg = GA.getOperand(0).getReg(); in getCompoundOpcode()
3526 const MachineOperand &CmpOp = GA.getOperand(2); in getCompoundOpcode()
3775 const MachineOperand &BrTarget = MI.getOperand(1); in getDotNewPredJumpOp()
3938 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3939 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3945 MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
3946 isShiftedUInt<5,2>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3950 (MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
3951 isShiftedUInt<4,2>(MI.getOperand(2).getImm()))) in getDuplexCandidateGroup()
3958 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3959 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3961 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3979 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3980 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3982 MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
3983 isShiftedUInt<3,1>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3989 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
3990 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
3992 MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
3993 isUInt<3>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3999 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4000 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4004 MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
4005 isShiftedUInt<5,3>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4021 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4035 DstReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4036 SrcReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4050 SrcReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4063 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4064 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4067 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() && in getDuplexCandidateGroup()
4068 isShiftedUInt<5,2>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
4072 MI.getOperand(1).isImm() && in getDuplexCandidateGroup()
4073 isShiftedUInt<4,2>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
4079 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4080 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4082 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
4097 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4098 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4100 MI.getOperand(1).isImm() && in getDuplexCandidateGroup()
4101 isShiftedUInt<3,1>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
4107 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4108 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4111 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() && in getDuplexCandidateGroup()
4112 isShiftedInt<6,3>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
4118 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4119 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() && in getDuplexCandidateGroup()
4120 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) && in getDuplexCandidateGroup()
4121 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4127 Src1Reg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4129 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) && in getDuplexCandidateGroup()
4130 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4135 if (MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
4136 isShiftedUInt<5,3>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4159 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4160 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4164 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
4165 isShiftedUInt<6,2>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4168 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
4169 isInt<7>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4173 if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
4174 ((MI.getOperand(2).getImm() == 1) || in getDuplexCandidateGroup()
4175 (MI.getOperand(2).getImm() == -1))) in getDuplexCandidateGroup()
4182 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4183 Src1Reg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4184 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4194 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4195 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4197 MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
4198 ((MI.getOperand(2).getImm() == 1) || in getDuplexCandidateGroup()
4199 (MI.getOperand(2).getImm() == 255))) in getDuplexCandidateGroup()
4205 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4206 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4216 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4231 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4232 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4235 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) in getDuplexCandidateGroup()
4241 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4242 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4245 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4253 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4255 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) || in getDuplexCandidateGroup()
4256 (MI.getOperand(1).isGlobal() && in getDuplexCandidateGroup()
4257 isUInt<2>(MI.getOperand(1).getOffset()))) && in getDuplexCandidateGroup()
4258 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) || in getDuplexCandidateGroup()
4259 (MI.getOperand(2).isGlobal() && in getDuplexCandidateGroup()
4260 isUInt<2>(MI.getOperand(2).getOffset())))) in getDuplexCandidateGroup()
4267 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4268 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4270 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) || in getDuplexCandidateGroup()
4271 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0))) in getDuplexCandidateGroup()
4277 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4278 SrcReg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4280 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) || in getDuplexCandidateGroup()
4281 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0))) in getDuplexCandidateGroup()
4293 DstReg = MI.getOperand(0).getReg(); in getDuplexCandidateGroup()
4294 SrcReg = MI.getOperand(1).getReg(); in getDuplexCandidateGroup()
4333 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency()
4346 const MachineOperand &UseMO = UseMI.getOperand(UseIdx); in getOperandLatency()
4602 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef(); in getSize()
4606 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?"); in getSize()
4608 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName(); in getSize()
4647 MachineOperand &MO = MI.getOperand(ExtOpNum); in immediateExtend()
4665 while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB()) in invertAndChangeJumpTarget()
4667 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB()); in invertAndChangeJumpTarget()
4668 MI.getOperand(TargetPos).setMBB(NewTarget); in invertAndChangeJumpTarget()
4724 MachineOperand &Operand = MIB->getOperand(0); in setBundleNoShuf()
4733 const MachineOperand &Operand = MIB.getOperand(0); in getBundleNoShuf()