Lines Matching refs:getOperand
129 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
131 MI.getOperand(0).isRenamable() ? RegState::Renamable : 0; in expandMOVImm()
132 uint64_t Imm = MI.getOperand(1).getImm(); in expandMOVImm()
156 .add(MI.getOperand(0)) in expandMOVImm()
160 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
161 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
173 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
174 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
188 .add(MI.getOperand(0)) in expandMOVImm()
192 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
193 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
207 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
217 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
218 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
241 const MachineOperand &Dest = MI.getOperand(0); in expandCMP_SWAP()
242 Register StatusReg = MI.getOperand(1).getReg(); in expandCMP_SWAP()
243 bool StatusDead = MI.getOperand(1).isDead(); in expandCMP_SWAP()
246 assert(!MI.getOperand(2).isUndef() && "cannot handle undef"); in expandCMP_SWAP()
247 Register AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP()
248 Register DesiredReg = MI.getOperand(3).getReg(); in expandCMP_SWAP()
249 Register NewReg = MI.getOperand(4).getReg(); in expandCMP_SWAP()
320 MachineOperand &DestLo = MI.getOperand(0); in expandCMP_SWAP_128()
321 MachineOperand &DestHi = MI.getOperand(1); in expandCMP_SWAP_128()
322 Register StatusReg = MI.getOperand(2).getReg(); in expandCMP_SWAP_128()
323 bool StatusDead = MI.getOperand(2).isDead(); in expandCMP_SWAP_128()
326 assert(!MI.getOperand(3).isUndef() && "cannot handle undef"); in expandCMP_SWAP_128()
327 Register AddrReg = MI.getOperand(3).getReg(); in expandCMP_SWAP_128()
328 Register DesiredLoReg = MI.getOperand(4).getReg(); in expandCMP_SWAP_128()
329 Register DesiredHiReg = MI.getOperand(5).getReg(); in expandCMP_SWAP_128()
330 Register NewLoReg = MI.getOperand(6).getReg(); in expandCMP_SWAP_128()
331 Register NewHiReg = MI.getOperand(7).getReg(); in expandCMP_SWAP_128()
497 Register DstReg = MI.getOperand(0).getReg(); in expand_DestructiveOp()
498 bool DstIsDead = MI.getOperand(0).isDead(); in expand_DestructiveOp()
505 if (DstReg == MI.getOperand(3).getReg()) { in expand_DestructiveOp()
521 if (DstReg == MI.getOperand(3).getReg()) { in expand_DestructiveOp()
525 } else if (DstReg == MI.getOperand(4).getReg()) { in expand_DestructiveOp()
541 DOPRegIsUnique = DstReg != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp()
546 DstReg != MI.getOperand(DOPIdx).getReg() || in expand_DestructiveOp()
547 MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp()
555 DstReg != MI.getOperand(DOPIdx).getReg() || in expand_DestructiveOp()
556 (MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg() && in expand_DestructiveOp()
557 MI.getOperand(DOPIdx).getReg() != MI.getOperand(Src2Idx).getReg()); in expand_DestructiveOp()
618 .addReg(MI.getOperand(PredIdx).getReg()) in expand_DestructiveOp()
619 .addReg(MI.getOperand(DOPIdx).getReg()); in expand_DestructiveOp()
633 .add(MI.getOperand(PredIdx)) in expand_DestructiveOp()
637 } else if (DstReg != MI.getOperand(DOPIdx).getReg()) { in expand_DestructiveOp()
641 .addReg(MI.getOperand(DOPIdx).getReg()); in expand_DestructiveOp()
653 DOP.addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill) in expand_DestructiveOp()
654 .add(MI.getOperand(PredIdx)) in expand_DestructiveOp()
655 .add(MI.getOperand(SrcIdx)); in expand_DestructiveOp()
661 DOP.add(MI.getOperand(PredIdx)) in expand_DestructiveOp()
662 .addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill) in expand_DestructiveOp()
663 .add(MI.getOperand(SrcIdx)); in expand_DestructiveOp()
666 DOP.add(MI.getOperand(PredIdx)) in expand_DestructiveOp()
667 .addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill) in expand_DestructiveOp()
668 .add(MI.getOperand(SrcIdx)) in expand_DestructiveOp()
669 .add(MI.getOperand(Src2Idx)); in expand_DestructiveOp()
688 Register SizeReg = MI.getOperand(0).getReg(); in expandSetTagLoop()
689 Register AddressReg = MI.getOperand(1).getReg(); in expandSetTagLoop()
699 unsigned Size = MI.getOperand(2).getImm(); in expandSetTagLoop()
776 int ImmOffset = MI.getOperand(2).getImm() + Offset; in expandSVESpillFill()
777 bool Kill = (Offset + 1 == N) ? MI.getOperand(1).isKill() : false; in expandSVESpillFill()
781 .addReg(TRI->getSubReg(MI.getOperand(0).getReg(), sub0 + Offset), in expandSVESpillFill()
783 .addReg(MI.getOperand(1).getReg(), getKillRegState(Kill)) in expandSVESpillFill()
806 while (!MBBI->getOperand(RegMaskStartIdx).isRegMask()) { in createCallWithOps()
807 const MachineOperand &MOP = MBBI->getOperand(RegMaskStartIdx); in createCallWithOps()
843 MachineOperand &RVTarget = MI.getOperand(0); in expandCALL_RVMARKER()
850 const MachineOperand &CallTarget = MI.getOperand(1); in expandCALL_RVMARKER()
851 const MachineOperand &Key = MI.getOperand(2); in expandCALL_RVMARKER()
852 const MachineOperand &IntDisc = MI.getOperand(3); in expandCALL_RVMARKER()
853 const MachineOperand &AddrDisc = MI.getOperand(4); in expandCALL_RVMARKER()
865 OriginalCall = createCall(MBB, MBBI, TII, MI.getOperand(1), in expandCALL_RVMARKER()
897 MachineInstr *Call = createCall(MBB, MBBI, TII, MI.getOperand(0), in expandCALL_BTI()
919 Register CtxReg = MBBI->getOperand(0).getReg(); in expandStoreSwiftAsyncContext()
920 Register BaseReg = MBBI->getOperand(1).getReg(); in expandStoreSwiftAsyncContext()
921 int Offset = MBBI->getOperand(2).getImm(); in expandStoreSwiftAsyncContext()
986 .add(MI.getOperand(0)); in expandRestoreZA()
1007 MIB.addReg(MI.getOperand(1).getReg(), RegState::Implicit); in expandRestoreZA()
1009 MIB.add(MI.getOperand(I)); in expandRestoreZA()
1071 switch (MI.getOperand(2).getImm()) { in expandCondSMToggle()
1081 auto PStateSM = MI.getOperand(3).getReg(); in expandCondSMToggle()
1109 MIB.add(MI.getOperand(0)); in expandCondSMToggle()
1110 MIB.add(MI.getOperand(1)); in expandCondSMToggle()
1112 MIB.add(MI.getOperand(i)); in expandCondSMToggle()
1125 Register Tuple = MI.getOperand(0).getReg(); in expandMultiVecPseudo()
1138 .add(MI.getOperand(0)) in expandMultiVecPseudo()
1139 .add(MI.getOperand(1)) in expandMultiVecPseudo()
1140 .add(MI.getOperand(2)) in expandMultiVecPseudo()
1141 .add(MI.getOperand(3)); in expandMultiVecPseudo()
1171 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
1172 if (DstReg == MI.getOperand(3).getReg()) { in expandMI()
1177 .add(MI.getOperand(0)) in expandMI()
1178 .add(MI.getOperand(3)) in expandMI()
1179 .add(MI.getOperand(2)) in expandMI()
1180 .add(MI.getOperand(1)); in expandMI()
1181 } else if (DstReg == MI.getOperand(2).getReg()) { in expandMI()
1186 .add(MI.getOperand(0)) in expandMI()
1187 .add(MI.getOperand(2)) in expandMI()
1188 .add(MI.getOperand(3)) in expandMI()
1189 .add(MI.getOperand(1)); in expandMI()
1192 if (DstReg == MI.getOperand(1).getReg()) { in expandMI()
1196 .add(MI.getOperand(0)) in expandMI()
1197 .add(MI.getOperand(1)) in expandMI()
1198 .add(MI.getOperand(2)) in expandMI()
1199 .add(MI.getOperand(3)); in expandMI()
1206 getRenamableRegState(MI.getOperand(0).isRenamable())) in expandMI()
1207 .add(MI.getOperand(1)) in expandMI()
1208 .add(MI.getOperand(1)); in expandMI()
1212 .add(MI.getOperand(0)) in expandMI()
1215 getRenamableRegState(MI.getOperand(0).isRenamable())) in expandMI()
1216 .add(MI.getOperand(2)) in expandMI()
1217 .add(MI.getOperand(3)); in expandMI()
1284 MIB1.addReg(MI.getOperand(0).getReg(), RegState::Define) in expandMI()
1285 .add(MI.getOperand(1)) in expandMI()
1286 .add(MI.getOperand(2)) in expandMI()
1297 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
1298 const MachineOperand &MO1 = MI.getOperand(1); in expandMI()
1326 unsigned DstFlags = MI.getOperand(0).getTargetFlags(); in expandMI()
1332 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
1334 .add(MI.getOperand(0)) in expandMI()
1368 const BlockAddress *BA = MI.getOperand(1).getBlockAddress(); in expandMI()
1369 assert(MI.getOperand(1).getOffset() == 0 && "unexpected offset"); in expandMI()
1374 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
1395 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
1399 .add(MI.getOperand(1)); in expandMI()
1401 if (MI.getOperand(1).getTargetFlags() & AArch64II::MO_TAGGED) { in expandMI()
1409 auto Tag = MI.getOperand(1); in expandMI()
1420 .add(MI.getOperand(0)) in expandMI()
1422 .add(MI.getOperand(2)) in expandMI()
1432 .add(MI.getOperand(0)) in expandMI()
1433 .add(MI.getOperand(1)) in expandMI()
1434 .add(MI.getOperand(2)) in expandMI()
1440 Register DstReg = MI.getOperand(0).getReg(); in expandMI()
1506 .add(MI.getOperand(0)) in expandMI()
1507 .add(MI.getOperand(1)); in expandMI()
1530 SrcReg = MI.getOperand(0).getReg(); in expandMI()
1535 .add(MI.getOperand(0)) in expandMI()
1537 .add(MI.getOperand(2)); in expandMI()
1542 int64_t Offset = MI.getOperand(2).getImm(); in expandMI()
1545 .add(MI.getOperand(0)) in expandMI()
1546 .add(MI.getOperand(1)) in expandMI()
1548 .add(MI.getOperand(4)); in expandMI()