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/freebsd/sys/arm/xilinx/
H A Dzy7_slcr.c213 int div0, div1; in cgem_set_ref_clk() local
221 for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) { in cgem_set_ref_clk()
222 div0 = (io_pll_frequency + div1 * frequency / 2) / in cgem_set_ref_clk()
223 div1 / frequency; in cgem_set_ref_clk()
225 ((io_pll_frequency / div0 / div1) + 500) / 1000 == in cgem_set_ref_clk()
230 if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX) in cgem_set_ref_clk()
240 (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) | in cgem_set_ref_clk()
314 int div0, div1; in zy7_pl_fclk_set_freq() local
343 for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) { in zy7_pl_fclk_set_freq()
344 div0 = (base_frequency + div1 * frequency / 2) / in zy7_pl_fclk_set_freq()
[all …]
/freebsd/sys/arm/mv/clk/
H A Dperiph_clk_d.c66 struct clk_div_def *div1; in a37x0_periph_d_register_full_clk_dd() local
72 div1 = &device_def->clk_def.full_dd.div1; in a37x0_periph_d_register_full_clk_dd()
85 a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1); in a37x0_periph_d_register_full_clk_dd()
86 error = a37x0_periph_create_div(clkdom, div1, in a37x0_periph_d_register_full_clk_dd()
91 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); in a37x0_periph_d_register_full_clk_dd()
229 struct clk_div_def *div1; in a37x0_periph_d_register_mdd() local
235 div1 = &device_def->clk_def.mdd.div1; in a37x0_periph_d_register_mdd()
246 a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1); in a37x0_periph_d_register_mdd()
247 error = a37x0_periph_create_div(clkdom, div1, in a37x0_periph_d_register_mdd()
252 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); in a37x0_periph_d_register_mdd()
H A Dperiph.h71 .clk_def.full_dd.div1.clkdef.name = _div1_name, \
72 .clk_def.full_dd.div1.offset = _div1_reg, \
73 .clk_def.full_dd.div1.i_shift = _div1_shift, \
74 .clk_def.full_dd.div1.i_width = 0x3, \
75 .clk_def.full_dd.div1.f_shift = 0x0, \
76 .clk_def.full_dd.div1.f_width = 0x0, \
77 .clk_def.full_dd.div1.div_flags = 0x0, \
78 .clk_def.full_dd.div1.div_table = NULL, \
189 .clk_def.mdd.div1.clkdef.name = _div1_name, \
190 .clk_def.mdd.div1.offset = _div1_reg, \
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddpll.txt41 "mult-div1" - contains the multiplier / divider register base address
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8996-oneplus-common.dtsi34 div1_mclk: div1-clk {
H A Dapq8096-db820c.dts545 audio_mclk: clk-div1-state {