Lines Matching refs:div1
213 int div0, div1; in cgem_set_ref_clk() local
221 for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) { in cgem_set_ref_clk()
222 div0 = (io_pll_frequency + div1 * frequency / 2) / in cgem_set_ref_clk()
223 div1 / frequency; in cgem_set_ref_clk()
225 ((io_pll_frequency / div0 / div1) + 500) / 1000 == in cgem_set_ref_clk()
230 if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX) in cgem_set_ref_clk()
240 (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) | in cgem_set_ref_clk()
314 int div0, div1; in zy7_pl_fclk_set_freq() local
343 for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) { in zy7_pl_fclk_set_freq()
344 div0 = (base_frequency + div1 * frequency / 2) / in zy7_pl_fclk_set_freq()
345 div1 / frequency; in zy7_pl_fclk_set_freq()
347 ((base_frequency / div0 / div1) + 500) / 1000 == in zy7_pl_fclk_set_freq()
352 if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX) in zy7_pl_fclk_set_freq()
364 reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) | in zy7_pl_fclk_set_freq()
373 return (base_frequency / div0 / div1); in zy7_pl_fclk_set_freq()
380 int div0, div1; in zy7_pl_fclk_get_freq() local
411 div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >> in zy7_pl_fclk_get_freq()
421 if (div1 == 0) in zy7_pl_fclk_get_freq()
422 div1 = 1; in zy7_pl_fclk_get_freq()
424 frequency = (base_frequency / div0 / div1); in zy7_pl_fclk_get_freq()