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Searched refs:bypass (Results 1 – 25 of 139) sorted by relevance

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/freebsd/sys/netgraph/netflow/
H A Dng_netflow.c597 uint8_t acct = 0, bypass = 0; in ng_netflow_rcvdata() local
619 bypass = 1; in ng_netflow_rcvdata()
623 bypass = 1; in ng_netflow_rcvdata()
628 if ((!bypass) && (iface->info.conf & in ng_netflow_rcvdata()
635 bypass = 1; in ng_netflow_rcvdata()
643 if (bypass) { in ng_netflow_rcvdata()
688 goto bypass; \ in ng_netflow_rcvdata()
755 goto bypass; /* pass this frame */ in ng_netflow_rcvdata()
779 goto bypass; in ng_netflow_rcvdata()
790 goto bypass; in ng_netflow_rcvdata()
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/freebsd/sys/contrib/device-tree/Bindings/c6x/
H A Dclocks.txt24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
37 ti,c64x+pll-bypass-delay = <200>;
/freebsd/sys/dev/ixgbe/
H A Dif_bypass.c47 while (atomic_cmpset_int(&sc->bypass.low, 0, 1) == 0) in ixgbe_bypass_mutex_enter()
49 while (atomic_cmpset_int(&sc->bypass.high, 0, 1) == 0) in ixgbe_bypass_mutex_enter()
60 while (atomic_cmpset_int(&sc->bypass.high, 1, 0) == 0) in ixgbe_bypass_mutex_clear()
62 while (atomic_cmpset_int(&sc->bypass.low, 1, 0) == 0) in ixgbe_bypass_mutex_clear()
75 while (atomic_cmpset_int(&sc->bypass.high, 0, 1) == 0) in ixgbe_bypass_wd_mutex_enter()
86 while (atomic_cmpset_int(&sc->bypass.high, 1, 0) == 0) in ixgbe_bypass_wd_mutex_clear()
565 while (atomic_cmpset_int(&sc->bypass.log, 0, 1) == 0) in ixgbe_bp_log()
695 while (atomic_cmpset_int(&sc->bypass.log, 1, 0) == 0) in ixgbe_bp_log()
702 while (atomic_cmpset_int(&sc->bypass.log, 1, 0) == 0) in ixgbe_bp_log()
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddpll.txt5 (reference clock and bypass clock), with digital phase locked
36 and second entry bypass clock
55 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
79 ti,low-power-bypass;
H A Dfapll.txt5 (reference clock and bypass clock), and one or more child
13 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
H A Dapll.txt5 (reference clock and bypass clock), with analog phase locked
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dat91-clock.txt20 - atmel,osc-bypass : boolean property. Set this when a clock signal is directly
47 - atmel,osc-bypass : boolean property. Set this when a clock signal is directly
/freebsd/sys/netgraph/
H A Dng_checksum.c555 goto bypass; \ in ng_checksum_rcvdata()
565 goto bypass; in ng_checksum_rcvdata()
635 goto bypass; in ng_checksum_rcvdata()
646 goto bypass; in ng_checksum_rcvdata()
664 bypass: in ng_checksum_rcvdata()
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra72-evm-tps65917.dtsi86 regulator-allow-bypass;
93 regulator-allow-bypass;
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetItinerary.td28 // Pipeline bypass / forwarding - These values specifies the symbolic names of
95 // a def by an instruction is available on a specific bypass and the use can
96 // read from the same bypass, then the operand use latency is reduced by one.
144 // info. Subtargets using NoItineraries can bypass the scheduler's
/freebsd/contrib/sendmail/cf/mailer/
H A Dlocal.m442 R@ <@ $*> $n temporarily bypass Sun bogosity
62 R@ <@ $*> $n temporarily bypass Sun bogosity
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt32 - single-ulpi-bypass: Must be present if the controller contains a single
33 ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
/freebsd/sys/dev/safe/
H A Dsafe.c769 int bypass, oplen; in safe_process() local
905 bypass = crp->crp_aad_start; in safe_process()
907 bypass = crp->crp_payload_start; in safe_process()
919 bypass, coffset, oplen); in safe_process()
953 bypass = crp->crp_payload_start; in safe_process()
954 oplen = bypass + crp->crp_payload_length; in safe_process()
958 if (bypass > 96) { /* bypass offset must be <= 96 bytes */ in safe_process()
959 DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); in safe_process()
1227 | (bypass << SAFE_PE_LEN_BYPASS_S) in safe_process()
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ul-ccimx6ulsom.dtsi263 regulator-allow-bypass;
268 regulator-allow-bypass;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleE500mc.td27 // The CFX has a bypass path, allowing non-divide instructions to execute
33 : FuncUnit; // CFX divide bypass path
327 let LoadLatency = 5; // Optimistic load latency assuming bypass.
H A DPPCScheduleE5500.td27 // The CFX has a bypass path, allowing non-divide instructions to execute
33 : FuncUnit; // CFX divide bypass path
371 let LoadLatency = 6; // Optimistic load latency assuming bypass.
/freebsd/sys/contrib/device-tree/src/c6x/
H A Dtms320c6457.dtsi64 ti,c64x+pll-bypass-delay = <300>;
H A Dtms320c6474.dtsi85 ti,c64x+pll-bypass-delay = <120>;
H A Dtms320c6455.dtsi74 ti,c64x+pll-bypass-delay = <1440>;
H A Dtms320c6472.dtsi108 ti,c64x+pll-bypass-delay = <200>;
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dsprd,sc2731-regulator.txt5 their own bypass (power-down) control signals. External tantalum or MLCC
/freebsd/sys/contrib/ncsw/Peripherals/FM/Rtc/
H A Dfm_rtc.c180 p_Rtc->p_RtcDriverParam->bypass = DEFAULT_BYPASS; in FM_RTC_Config()
218 if (!p_RtcDriverParam->timer_slave_mode && p_Rtc->p_RtcDriverParam->bypass) in FM_RTC_Init()
318 p_Rtc->p_RtcDriverParam->bypass = enabled; in FM_RTC_ConfigFrequencyBypass()
/freebsd/contrib/expat/
H A DMakefile.am127 @echo 'ERROR: "make -C lib all install" to bypass compilation' >&2
/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dsja1000.txt45 - nxp,no-comparator-bypass : Allows to disable the CAN input comparator.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86.td565 // Goldmont / Tremont (atom in general) has no bypass delay
566 def TuningNoDomainDelay : SubtargetFeature<"no-bypass-delay",
568 "Has no bypass delay when using the 'wrong' domain">;
570 // Many processors (Nehalem+ on Intel) have no bypass delay when
572 def TuningNoDomainDelayMov : SubtargetFeature<"no-bypass-delay-mov",
574 "Has no bypass delay when using the 'wrong' mov type">;
576 // Newer processors (Skylake+ on Intel) have no bypass delay when
578 def TuningNoDomainDelayBlend : SubtargetFeature<"no-bypass-delay-blend",
580 "Has no bypass delay when using the 'wrong' blend type">;
582 // Newer processors (Haswell+ on Intel) have no bypass delay when
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