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Searched refs:buildCopy (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp177 auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg()); in assignCustomValue()
178 auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg()); in assignCustomValue()
224 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
237 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); in getStackAddress()
283 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
284 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
288 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
289 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
430 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I])); in lowerFormalArguments()
537 MIRBuilder.buildCopy( in lowerCall()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp109 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
380 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, in buildCopy() function in X86AvoidSFBPass
440 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, in buildCopies()
451 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, in buildCopies()
461 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, in buildCopies()
471 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, in buildCopies()
481 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, in buildCopies()
H A DX86CallLowering.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp99 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
113 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
157 MIRBuilder.buildCopy(RetReg, FLI.DemoteRegister); in lowerReturn()
160 MIRBuilder.buildCopy(RetReg, Reg); in lowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp63 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
83 auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0); in getStackAddress()
186 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUGlobalISelDivergenceLowering.cpp136 B.buildCopy(LaneMask, Reg); in buildRegCopyToLaneMask()
186 auto Copy = B.buildCopy(LLT::scalar(1), In.Reg); in constrainAsLaneMask()
H A DAMDGPUCallLowering.cpp93 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
127 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
215 SPReg = MIRBuilder.buildCopy(PtrTy, in getStackAddress()
237 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
490 B.buildCopy(VReg, InputPtrReg); in allocateHSAUserSGPRs()
1163 auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32), in handleImplicitCallArguments()
1170 MIRBuilder.buildCopy(CalleeRSrcReg, ScratchRSrcReg); in handleImplicitCallArguments()
1175 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second); in handleImplicitCallArguments()
H A DAMDGPURegisterBankInfo.cpp717 Src = B.buildCopy(Ty, Src).getReg(0); in buildReadFirstLane()
886 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
1203 auto SPCopy = B.buildCopy(PtrTy, SPReg); in applyMappingDynStackAlloc()
1320 VOffsetReg = B.buildCopy(S32, CombinedOffset).getReg(0); in setBufferOffsets()
1594 Register VSrc0 = B.buildCopy(S32, Src0).getReg(0); in applyMappingMAD_64_32()
1595 Register VSrc1 = B.buildCopy(S32, Src1).getReg(0); in applyMappingMAD_64_32()
1644 DstLo = B.buildCopy(S32, DstLo).getReg(0); in applyMappingMAD_64_32()
1645 DstHi = B.buildCopy(S32, DstHi).getReg(0); in applyMappingMAD_64_32()
1693 B.buildCopy(Dst1, Carry); in applyMappingMAD_64_32()
1908 B.buildCopy(Hi32Reg, Lo32Reg); in extendLow32IntoHigh32()
[all …]
H A DAMDGPURegBankCombiner.cpp144 Register VgprReg = B.buildCopy(MRI.getType(Reg), Reg).getReg(0); in getAsVgpr()
H A DAMDGPULegalizerInfo.cpp2375 B.buildCopy(Dst, BuildPtr); in legalizeAddrSpaceCast()
2743 B.buildCopy(Dst, Unmerge.getReg(IdxVal)); in legalizeExtractVectorElt()
3442 B.buildCopy(Dst, R); in legalizeFlogCommon()
3725 B.buildCopy(Dst, R); in legalizeFExp()
4286 B.buildCopy(DstReg, LiveIn); in loadInputValue()
5133 B.buildCopy(Res0, Mant); in legalizeFFREXP()
6864 B.buildCopy(SGPR01, Temp); in legalizeTrapHsaQueuePtr()
6879 B.buildCopy(SGPR01, LiveIn); in legalizeTrapHsaQueuePtr()
7119 auto TTMP8 = B.buildCopy(S32, Register(AMDGPU::TTMP8)); in legalizeWaveID()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp109 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress()
128 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
305 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
312 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); in assignValueToReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp211 MIRBuilder.buildCopy(Dst, Src); in buildAnyextOrCopy()
592 MIRBuilder.buildCopy(Tmp1Reg, SrcReg); in lowerInlineAsm()
596 MIRBuilder.buildCopy(ResRegs[i], SrcReg); in lowerInlineAsm()
H A DIRTranslator.cpp346 MIRBuilder.buildCopy( in translateCompare()
349 MIRBuilder.buildCopy( in translateCompare()
1381 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
1429 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1537 MIRBuilder.buildCopy(Regs[0], Src); in translateCopy()
1680 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
2416 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2510 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2643 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt( in translateCallBase()
3017 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
[all …]
H A DLegalizerHelper.cpp1311 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); in narrowScalar()
3898 MIRBuilder.buildCopy(OldValRes, NewOldValRes); in lower()
3922 MIRBuilder.buildCopy(Res, NewRes); in lower()
3952 MIRBuilder.buildCopy(Res, NewRes); in lower()
5087 MIRBuilder.buildCopy(DstReg, SplitSrcs[0]); in fewerElementsVectorReductions()
5096 MIRBuilder.buildCopy(DstReg, Acc); in fewerElementsVectorReductions()
5154 MIRBuilder.buildCopy(DstReg, Acc); in fewerElementsVectorSeqReductions()
6086 MIRBuilder.buildCopy(DstReg, DstRegs[0]); in narrowScalarExtract()
6791 MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Merge.getReg(0)); in lowerTRUNC()
7549 MIRBuilder.buildCopy(DstReg, SrcRegs[IdxVal]); in lowerExtractInsertVectorElt()
[all …]
H A DMachineIRBuilder.cpp285 return buildCopy(Res, Unmerge.getReg(0)); in buildDeleteTrailingVectorElements()
312 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy() function in MachineIRBuilder
541 return buildCopy(Res, Op); in buildBoolExtInReg()
600 return buildCopy(Dst, Src); in buildCast()
H A DCombinerHelperVectorOps.cpp203 B.buildCopy(Dst, Build->getSourceReg(MaybeIndex->Value.getZExtValue())); in matchExtractVectorElementWithBuildVector()
H A DCSEMIRBuilder.cpp155 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
H A DCallLowering.cpp907 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr); in handleAssignments()
1391 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
1395 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg); in assignValueToReg()
H A DCombinerHelper.cpp171 Builder.buildCopy(ToReg, FromReg); in replaceRegWith()
274 B.buildCopy(DstOp, OrigOp); in matchFreezeOfSingleMaybePoisonOperand()
452 Builder.buildCopy(MI.getOperand(0).getReg(), Ops[0]); in applyCombineShuffleConcat()
548 Builder.buildCopy(NewDstReg, Ops[0]); in applyCombineShuffleVector()
582 Builder.buildCopy(DstReg, SrcReg); in applyShuffleToExtract()
1025 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
2156 SrcReg = Builder.buildCopy(MRI.getType(SrcReg), SrcReg).getReg(0); in applyCombineUnmergeMergeToPlainValues()
2421 Builder.buildCopy(DstReg, Reg); in applyCombineI2PToP2I()
5143 MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, ReplaceReg); }; in matchSubAddSameReg()
7295 B.buildCopy(Dst, LHS); in matchAddOverflow()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp271 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
296 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
467 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
525 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
1227 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
1459 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
H A DAArch64InstructionSelector.cpp1045 auto Copy = MIB.buildCopy({DstTempRC}, {SrcReg}); in selectCopy()
2085 auto Copy = MIB.buildCopy(LLT::scalar(64), SrcOp); in preISelLower()
2112 auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(1).getReg()); in preISelLower()
2676 MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()}); in select()
2689 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
3490 MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X16)); in select()
3602 MIB.buildCopy(DstPtrCopy, DstPtr); in selectMOPS()
3603 MIB.buildCopy(SrcValCopy, SrcOrVal); in selectMOPS()
3604 MIB.buildCopy(SizeCopy, Size); in selectMOPS()
3649 MIB.buildCopy({AArch64::X16}, I.getOperand(2).getReg()); in selectBrJT()
[all …]
H A DAArch64PostLegalizerCombiner.cpp244 B.buildCopy(DstReg, Res.getReg(0)); in matchAArch64MulConstCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp55 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DSplitKit.h432 SlotIndex buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp78 SPReg = MIRBuilder.buildCopy(p0, Register(RISCV::X2)).getReg(0); in getStackAddress()
115 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()

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