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Searched refs:buildCopy (Results 1 – 25 of 38) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp177 auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg()); in assignCustomValue()
178 auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg()); in assignCustomValue()
224 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
237 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); in getStackAddress()
283 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
284 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
288 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
289 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
428 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I])); in lowerFormalArguments()
535 MIRBuilder.buildCopy( in lowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp108 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
379 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, in buildCopy() function in X86AvoidSFBPass
439 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, in buildCopies()
450 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, in buildCopies()
460 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, in buildCopies()
470 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, in buildCopies()
480 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, in buildCopies()
H A DX86CallLowering.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp98 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
112 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
156 MIRBuilder.buildCopy(RetReg, FLI.DemoteRegister); in lowerReturn()
159 MIRBuilder.buildCopy(RetReg, Reg); in lowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp63 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
83 auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0); in getStackAddress()
186 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp109 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress()
128 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
305 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
312 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); in assignValueToReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankSelect.cpp142 B.buildCopy(Reg, NewReg); in reAssignRegBankOnDef()
184 B.buildCopy(NewReg, Reg); in constrainRegBankUse()
H A DAMDGPUGlobalISelDivergenceLowering.cpp137 B.buildCopy(LaneMask, Reg); in buildRegCopyToLaneMask()
187 auto Copy = B.buildCopy(LLT::scalar(1), In.Reg); in constrainAsLaneMask()
H A DAMDGPURegBankLegalizeHelper.cpp316 {B.buildCopy(Ty, Src), B.buildCopy(S32, Src1)}); in lowerS_BFE()
321 B.buildCopy(DstReg, S_BFE->getOperand(0).getReg()); in lowerS_BFE()
904 auto CopyToVgpr = B.buildCopy({VgprRB, Ty}, Reg); in applyMappingSrc()
921 auto CopyToVgpr = B.buildCopy({VgprRB, Ty}, Reg); in applyMappingSrc()
1057 auto Copy = B.buildCopy({VgprRB, MRI.getType(Reg)}, Reg); in applyMappingTrivial()
H A DAMDGPUCallLowering.cpp92 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
126 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
214 SPReg = MIRBuilder.buildCopy(PtrTy, in getStackAddress()
480 B.buildCopy(VReg, InputPtrReg); in allocateHSAUserSGPRs()
1166 auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32), in handleImplicitCallArguments()
1173 MIRBuilder.buildCopy(CalleeRSrcReg, ScratchRSrcReg); in handleImplicitCallArguments()
1178 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second); in handleImplicitCallArguments()
H A DAMDGPURegisterBankInfo.cpp717 Src = B.buildCopy(Ty, Src).getReg(0); in buildReadFirstLane()
886 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
1210 auto OldSP = B.buildCopy(PtrTy, SPReg); in applyMappingDynStackAlloc()
1218 B.buildCopy(Dst, OldSP); in applyMappingDynStackAlloc()
1221 B.buildCopy(SPReg, PtrAdd); in applyMappingDynStackAlloc()
1330 VOffsetReg = B.buildCopy(S32, CombinedOffset).getReg(0); in setBufferOffsets()
1622 Register VSrc0 = B.buildCopy(S32, Src0).getReg(0); in applyMappingMAD_64_32()
1623 Register VSrc1 = B.buildCopy(S32, Src1).getReg(0); in applyMappingMAD_64_32()
1672 DstLo = B.buildCopy(S32, DstLo).getReg(0); in applyMappingMAD_64_32()
1673 DstHi = B.buildCopy(S32, DstHi).getReg(0); in applyMappingMAD_64_32()
[all …]
H A DAMDGPURegBankCombiner.cpp144 Register VgprReg = B.buildCopy(MRI.getType(Reg), Reg).getReg(0); in getAsVgpr()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelperCasts.cpp60 MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); }; in matchSextOfTrunc()
93 MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); }; in matchZextOfTrunc()
153 MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); }; in matchTruncateOfExt()
H A DInlineAsmLowering.cpp211 MIRBuilder.buildCopy(Dst, Src); in buildAnyextOrCopy()
592 MIRBuilder.buildCopy(Tmp1Reg, SrcReg); in lowerInlineAsm()
596 MIRBuilder.buildCopy(ResRegs[i], SrcReg); in lowerInlineAsm()
H A DIRTranslator.cpp364 MIRBuilder.buildCopy( in translateCompare()
367 MIRBuilder.buildCopy( in translateCompare()
1395 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
1443 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1550 MIRBuilder.buildCopy(Regs[0], Src); in translateCopy()
1692 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
2453 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2547 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2693 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt( in translateCallBase()
3064 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
[all …]
H A DCombinerHelperVectorOps.cpp182 B.buildCopy(Dst, Build->getSourceReg(Index.getZExtValue())); in matchExtractVectorElementWithBuildVector()
H A DMachineIRBuilder.cpp285 return buildCopy(Res, Unmerge.getReg(0)); in buildDeleteTrailingVectorElements()
312 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy() function in MachineIRBuilder
543 return buildCopy(Res, Op); in buildBoolExtInReg()
602 return buildCopy(Dst, Src); in buildCast()
H A DCSEMIRBuilder.cpp159 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
H A DLegalizerHelper.cpp1574 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); in narrowScalar()
4554 MIRBuilder.buildCopy(OldValRes, NewOldValRes); in lower()
4578 MIRBuilder.buildCopy(Res, NewRes); in lower()
4608 MIRBuilder.buildCopy(Res, NewRes); in lower()
5776 MIRBuilder.buildCopy(DstReg, SplitSrcs[0]); in fewerElementsVectorReductions()
5785 MIRBuilder.buildCopy(DstReg, Acc); in fewerElementsVectorReductions()
5843 MIRBuilder.buildCopy(DstReg, Acc); in fewerElementsVectorSeqReductions()
6778 MIRBuilder.buildCopy(DstReg, DstRegs[0]); in narrowScalarExtract()
7480 MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Merge.getReg(0)); in lowerTRUNC()
8470 MIRBuilder.buildCopy(DstReg, SrcRegs[IdxVal]); in lowerExtractInsertVectorElt()
[all …]
H A DCallLowering.cpp906 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr); in handleAssignments()
1390 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
1394 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg); in assignValueToReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp70 SPReg = MIRBuilder.buildCopy(p0, Register(RISCV::X2)).getReg(0); in getStackAddress()
98 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
112 MIRBuilder.buildCopy(PhysReg, Trunc); in assignCustomValue()
250 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg); in assignCustomValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp273 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
298 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
516 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
574 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
1276 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
1514 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
H A DAArch64InstructionSelector.cpp1053 auto Copy = MIB.buildCopy({DstTempRC}, {SrcReg}); in selectCopy()
2192 auto Copy = MIB.buildCopy(LLT::scalar(64), SrcOp); in preISelLower()
2225 auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(1).getReg()); in preISelLower()
2238 auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(2).getReg()); in preISelLower()
2805 MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()}); in select()
2818 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
3625 MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X16)); in select()
3737 MIB.buildCopy(DstPtrCopy, DstPtr); in selectMOPS()
3738 MIB.buildCopy(SrcValCopy, SrcOrVal); in selectMOPS()
3739 MIB.buildCopy(SizeCopy, Size); in selectMOPS()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp52 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DSplitKit.h438 SlotIndex buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask,

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