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Searched refs:VirtReg (Results 1 – 25 of 47) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp104 void LiveRegMatrix::assign(const LiveInterval &VirtReg, MCRegister PhysReg) { in assign() argument
105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg(), TRI) << " to " in assign()
107 assert(!VRM->hasPhys(VirtReg.reg()) && "Duplicate VirtReg assignment"); in assign()
108 VRM->assignVirt2Phys(VirtReg.reg(), PhysReg); in assign()
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
113 Matrix[Unit].unify(VirtReg, Range); in assign()
121 void LiveRegMatrix::unassign(const LiveInterval &VirtReg) { in unassign() argument
122 Register PhysReg = VRM->getPhys(VirtReg.reg()); in unassign()
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg(), TRI) in unassign()
125 VRM->clearVirt(VirtReg.reg()); in unassign()
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H A DRegAllocFast.cpp202 Register VirtReg; ///< Virtual register number. member
208 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
211 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
351 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg() argument
352 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
355 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { in findLiveVirtReg()
356 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
363 void assignDanglingDebugValues(MachineInstr &Def, Register VirtReg,
366 Register VirtReg);
367 bool defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
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H A DRegAllocBasic.cpp99 MCRegister selectOrSplit(const LiveInterval &VirtReg,
118 bool spillInterferences(const LiveInterval &VirtReg, MCRegister PhysReg,
146 bool RABasic::LRE_CanEraseVirtReg(Register VirtReg) { in INITIALIZE_PASS_DEPENDENCY()
147 LiveInterval &LI = LIS->getInterval(VirtReg); in INITIALIZE_PASS_DEPENDENCY()
148 if (VRM->hasPhys(VirtReg)) { in INITIALIZE_PASS_DEPENDENCY()
161 void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg() argument
162 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
166 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
206 bool RABasic::spillInterferences(const LiveInterval &VirtReg, in spillInterferences() argument
215 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in spillInterferences()
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H A DRegAllocGreedy.cpp234 bool RAGreedy::LRE_CanEraseVirtReg(Register VirtReg) { in LRE_CanEraseVirtReg() argument
235 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_CanEraseVirtReg()
236 if (VRM->hasPhys(VirtReg)) { in LRE_CanEraseVirtReg()
249 void RAGreedy::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg() argument
250 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
254 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
397 MCRegister RAGreedy::tryAssign(const LiveInterval &VirtReg, in tryAssign() argument
404 if (!Matrix->checkInterference(VirtReg, *I)) { in tryAssign()
418 if (Register Hint = MRI->getSimpleHint(VirtReg.reg())) in tryAssign()
423 if (EvictAdvisor->canEvictHintInterference(VirtReg, PhysHint, in tryAssign()
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H A DRegAllocBase.cpp89 while (const LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
90 assert(!VRM->hasPhys(VirtReg->reg()) && "Register already assigned"); in allocatePhysRegs()
93 if (MRI->reg_nodbg_empty(VirtReg->reg())) { in allocatePhysRegs()
94 LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); in allocatePhysRegs()
95 aboutToRemoveInterval(*VirtReg); in allocatePhysRegs()
96 LIS->removeInterval(VirtReg->reg()); in allocatePhysRegs()
107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg())) in allocatePhysRegs()
108 << ':' << *VirtReg << " w=" << VirtReg->weight() << '\n'); in allocatePhysRegs()
113 MCRegister AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); in allocatePhysRegs()
119 for (MachineInstr &MIR : MRI->reg_instructions(VirtReg->reg())) { in allocatePhysRegs()
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H A DRegAllocEvictionAdvisor.cpp169 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference() argument
173 return canEvictInterferenceBasedOnCost(VirtReg, PhysReg, true, MaxCost, in canEvictHintInterference()
187 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in canEvictInterferenceBasedOnCost() argument
190 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) in canEvictInterferenceBasedOnCost()
193 bool IsLocal = VirtReg.empty() || LIS->intervalIsInOneMBB(VirtReg); in canEvictInterferenceBasedOnCost()
202 unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg()); in canEvictInterferenceBasedOnCost()
206 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in canEvictInterferenceBasedOnCost()
233 !VirtReg.isSpillable() && in canEvictInterferenceBasedOnCost()
235 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < in canEvictInterferenceBasedOnCost()
261 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint)) in canEvictInterferenceBasedOnCost()
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H A DLiveIntervalUnion.cpp28 void LiveIntervalUnion::unify(const LiveInterval &VirtReg,
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
56 void LiveIntervalUnion::extract(const LiveInterval &VirtReg,
68 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); in extract()
116 const LiveInterval *VirtReg) const { in isSeenInterference()
117 return is_contained(InterferingVRegs, VirtReg); in isSeenInterference()
29 unify(const LiveInterval & VirtReg,const LiveRange & Range) unify() argument
57 extract(const LiveInterval & VirtReg,const LiveRange & Range) extract() argument
H A DMLRegallocEvictAdvisor.cpp
H A DMLRegAllocEvictAdvisor.cpp307 tryFindEvictionCandidatePosition(const LiveInterval &VirtReg,
315 loadInterferenceFeatures(const LiveInterval &VirtReg, MCRegister PhysReg,
324 const LiveInterval &VirtReg, const AllocationOrder &Order,
336 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference() argument
338 return getDefaultAdvisor().canEvictHintInterference(VirtReg, PhysReg, in canEvictHintInterference()
441 const LiveInterval &VirtReg, const AllocationOrder &Order,
600 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in loadInterferenceFeatures() argument
605 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) { in loadInterferenceFeatures()
610 const bool IsLocal = LIS->intervalIsInOneMBB(VirtReg); in loadInterferenceFeatures()
615 unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg()); in loadInterferenceFeatures()
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H A DRegAllocGreedy.h86 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage() argument
87 return getStage(VirtReg.reg()); in getStage()
95 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
96 setStage(VirtReg.reg(), Stage); in setStage()
338 const LiveInterval &VirtReg,
356 unsigned calculateRegionSplitCost(const LiveInterval &VirtReg,
361 unsigned doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
364 bool trySplitAroundHintReg(MCPhysReg Hint, const LiveInterval &VirtReg,
369 MCRegister tryAssignCSRFirstTime(const LiveInterval &VirtReg,
H A DVirtRegMap.cpp109 bool VirtRegMap::hasPreferredPhys(Register VirtReg) const { in hasPreferredPhys()
110 Register Hint = MRI->getSimpleHint(VirtReg); in hasPreferredPhys()
115 return Register(getPhys(VirtReg)) == Hint; in hasPreferredPhys()
118 bool VirtRegMap::hasKnownPreference(Register VirtReg) const { in hasKnownPreference()
119 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VirtReg); in hasKnownPreference()
342 Register VirtReg = Register::index2VirtReg(Idx); in addMBBLiveIns() local
343 if (MRI->reg_nodbg_empty(VirtReg)) in addMBBLiveIns()
345 LiveInterval &LI = LIS->getInterval(VirtReg); in addMBBLiveIns()
350 Register PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns()
552 Register VirtReg = MO.getReg(); in rewrite() local
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H A DAllocationOrder.cpp29 AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, in create() argument
34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in create()
H A DRegAllocEvictionAdvisor.h108 const LiveInterval &VirtReg, const AllocationOrder &Order,
114 canEvictHintInterference(const LiveInterval &VirtReg, MCRegister PhysReg,
124 bool canReassign(const LiveInterval &VirtReg, MCRegister FromReg) const;
128 std::optional<unsigned> getOrderLimit(const LiveInterval &VirtReg,
H A DRegisterCoalescer.h64 CoalescerPair(Register VirtReg, MCRegister PhysReg, in CoalescerPair() argument
66 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {} in CoalescerPair()
H A DLiveDebugVariables.cpp591 UserValue *lookupVirtReg(Register VirtReg);
659 void mapVirtReg(Register VirtReg, UserValue *EC);
788 void LDVImpl::mapVirtReg(Register VirtReg, UserValue *EC) { in mapVirtReg() argument
789 assert(VirtReg.isVirtual() && "Only map VirtRegs"); in mapVirtReg()
790 UserValue *&Leader = virtRegToEqClass[VirtReg]; in mapVirtReg()
794 UserValue *LDVImpl::lookupVirtReg(Register VirtReg) { in lookupVirtReg() argument
795 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg)) in lookupVirtReg()
1531 Register VirtReg = Loc.getReg(); in rewriteLocations() local
1532 if (VRM.isAssignedReg(VirtReg) && in rewriteLocations()
1533 Register::isPhysicalRegister(VRM.getPhys(VirtReg))) { in rewriteLocations()
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H A DTargetRegisterInfo.cpp67 const MachineFunction &MF, const LiveInterval &VirtReg) const { in shouldRegionSplitForVirtReg()
70 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg()); in shouldRegionSplitForVirtReg()
72 VirtReg.size() > HugeSizeForSplit) in shouldRegionSplitForVirtReg()
420 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
425 MRI.getRegAllocationHints(VirtReg); in getRegAllocationHints()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRegMatrix.h107 InterferenceKind checkInterference(const LiveInterval &VirtReg,
120 void assign(const LiveInterval &VirtReg, MCRegister PhysReg);
125 void unassign(const LiveInterval &VirtReg);
140 bool checkRegMaskInterference(const LiveInterval &VirtReg,
146 bool checkRegUnitInterference(const LiveInterval &VirtReg,
H A DVirtRegMap.h145 bool hasPreferredPhys(Register VirtReg) const;
150 bool hasKnownPreference(Register VirtReg) const;
169 Register getOriginal(Register VirtReg) const { in getOriginal() argument
170 Register Orig = getPreSplitReg(VirtReg); in getOriginal()
171 return Orig ? Orig : VirtReg; in getOriginal()
H A DLiveIntervalUnion.h91 void unify(const LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(const LiveInterval &VirtReg, const LiveRange &Range);
128 bool isSeenInterference(const LiveInterval *VirtReg) const;
H A DScheduleDAGInstrs.h53 unsigned VirtReg; member
58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit()
61 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastPreTileConfig.cpp68 int getStackSpaceFor(Register VirtReg);
70 bool mayLiveOut(Register VirtReg, MachineInstr *CfgMI);
71 void spill(MachineBasicBlock::iterator Before, Register VirtReg, bool Kill);
72 void reload(MachineBasicBlock::iterator UseMI, Register VirtReg,
118 int X86FastPreTileConfig::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor() argument
120 int SS = StackSlotForVirtReg[VirtReg]; in getStackSpaceFor()
126 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
132 StackSlotForVirtReg[VirtReg] = FrameIdx; in getStackSpaceFor()
139 bool X86FastPreTileConfig::mayLiveOut(Register VirtReg, MachineInstr *CfgMI) { in mayLiveOut() argument
140 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) in mayLiveOut()
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H A DX86TileConfig.cpp126 Register VirtReg = Register::index2VirtReg(I); in INITIALIZE_PASS_DEPENDENCY() local
127 if (MRI.reg_nodbg_empty(VirtReg)) in INITIALIZE_PASS_DEPENDENCY()
129 if (MRI.getRegClass(VirtReg)->getID() != X86::TILERegClassID) in INITIALIZE_PASS_DEPENDENCY()
131 if (VRM.getPhys(VirtReg) == VirtRegMap::NO_PHYS_REG) in INITIALIZE_PASS_DEPENDENCY()
133 unsigned Index = VRM.getPhys(VirtReg) - X86::TMM0; in INITIALIZE_PASS_DEPENDENCY()
135 Phys2Virt[Index] = VirtReg; in INITIALIZE_PASS_DEPENDENCY()
H A DX86RegisterInfo.cpp1035 static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, in getTileShape() argument
1037 if (VRM->hasShape(VirtReg)) in getTileShape()
1038 return VRM->getShape(VirtReg); in getTileShape()
1040 const MachineOperand &Def = *MRI->def_begin(VirtReg); in getTileShape()
1050 VRM->assignVirt2Shape(VirtReg, Shape); in getTileShape()
1068 VRM->assignVirt2Shape(VirtReg, Shape); in getTileShape()
1073 bool X86RegisterInfo::getRegAllocationHints(Register VirtReg, in getRegAllocationHints() argument
1080 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getRegAllocationHints()
1082 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
1088 ShapeT VirtShape = getTileShape(VirtReg, const_cast<VirtRegMap *>(VRM), MRI); in getRegAllocationHints()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
83 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
88 for (auto &Use : MRI->reg_nodbg_instructions(VirtReg)) in getRegAllocationHints()
93 if (VirtReg == Use.getOperand(0).getReg()) { in getRegAllocationHints()
98 } else if (VirtReg == Use.getOperand(1).getReg()) { in getRegAllocationHints()
101 } else if (VirtReg == Use.getOperand(2).getReg() && in getRegAllocationHints()
117 MRI->getRegClass(VirtReg)); in getRegAllocationHints()
131 if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) { in getRegAllocationHints()
134 Worklist.push_back(VirtReg); in getRegAllocationHints()
143 // VirtReg in getRegAllocationHints()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp125 const Register VirtReg = MO.getReg(); in rewriteRegs() local
126 if (VirtReg.isPhysical()) in rewriteRegs()
129 if (!VRM->hasPhys(VirtReg)) in rewriteRegs()
132 Register PhysReg = VRM->getPhys(VirtReg); in rewriteRegs()

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