Lines Matching refs:VirtReg
234 bool RAGreedy::LRE_CanEraseVirtReg(Register VirtReg) { in LRE_CanEraseVirtReg() argument
235 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_CanEraseVirtReg()
236 if (VRM->hasPhys(VirtReg)) { in LRE_CanEraseVirtReg()
249 void RAGreedy::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg() argument
250 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
254 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
397 MCRegister RAGreedy::tryAssign(const LiveInterval &VirtReg, in tryAssign() argument
404 if (!Matrix->checkInterference(VirtReg, *I)) { in tryAssign()
418 if (Register Hint = MRI->getSimpleHint(VirtReg.reg())) in tryAssign()
423 if (EvictAdvisor->canEvictHintInterference(VirtReg, PhysHint, in tryAssign()
425 evictInterference(VirtReg, PhysHint, NewVRegs); in tryAssign()
430 if (trySplitAroundHintReg(PhysHint, VirtReg, NewVRegs, Order)) in tryAssign()
435 SetOfBrokenHints.insert(&VirtReg); in tryAssign()
447 MCRegister CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters); in tryAssign()
455 bool RegAllocEvictionAdvisor::canReassign(const LiveInterval &VirtReg, in canReassign() argument
459 LiveIntervalUnion::Query SubQ(VirtReg, Matrix->getLiveUnions()[Unit]); in canReassign()
464 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix)) { in canReassign()
469 LLVM_DEBUG(dbgs() << "can reassign: " << VirtReg << " from " in canReassign()
481 void RAGreedy::evictInterference(const LiveInterval &VirtReg, in evictInterference() argument
487 unsigned Cascade = ExtraInfo->getOrAssignNewCascade(VirtReg.reg()); in evictInterference()
495 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in evictInterference()
512 VirtReg.isSpillable() < Intf->isSpillable()) && in evictInterference()
531 RegAllocEvictionAdvisor::getOrderLimit(const LiveInterval &VirtReg, in getOrderLimit() argument
538 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg()); in getOrderLimit()
577 MCRegister RAGreedy::tryEvict(const LiveInterval &VirtReg, in tryEvict() argument
586 VirtReg, Order, CostPerUseLimit, FixedRegisters); in tryEvict()
588 evictInterference(VirtReg, BestPhys, NewVRegs); in tryEvict()
1060 MCRegister RAGreedy::tryRegionSplit(const LiveInterval &VirtReg, in tryRegionSplit() argument
1063 if (!TRI->shouldRegionSplitForVirtReg(*MF, VirtReg)) in tryRegionSplit()
1083 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost, in tryRegionSplit()
1090 return doRegionSplit(VirtReg, BestCand, HasCompact, NewVRegs); in tryRegionSplit()
1171 unsigned RAGreedy::calculateRegionSplitCost(const LiveInterval &VirtReg, in calculateRegionSplitCost() argument
1189 unsigned RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand, in doRegionSplit() argument
1194 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in doRegionSplit()
1232 const LiveInterval &VirtReg, in trySplitAroundHintReg() argument
1242 if (ExtraInfo->getStage(VirtReg) >= RS_Split2) in trySplitAroundHintReg()
1246 Register Reg = VirtReg.reg(); in trySplitAroundHintReg()
1260 if (VirtReg.liveAt(LIS->getInstructionIndex(Instr).getRegSlot())) in trySplitAroundHintReg()
1277 SA->analyze(&VirtReg); in trySplitAroundHintReg()
1282 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs); in trySplitAroundHintReg()
1293 unsigned RAGreedy::tryBlockSplit(const LiveInterval &VirtReg, in tryBlockSplit() argument
1296 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed"); in tryBlockSplit()
1297 Register Reg = VirtReg.reg(); in tryBlockSplit()
1299 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryBlockSplit()
1382 const MachineInstr *MI, const LiveInterval &VirtReg, in readsLaneSubset() argument
1394 LaneBitmask ReadMask = getInstReadLaneMask(MRI, *TRI, *MI, VirtReg.reg()); in readsLaneSubset()
1397 for (const LiveInterval::SubRange &S : VirtReg.subranges()) { in readsLaneSubset()
1414 unsigned RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg, in tryInstructionSplit() argument
1417 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg()); in tryInstructionSplit()
1422 if (!VirtReg.hasSubRanges()) in tryInstructionSplit()
1429 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryInstructionSplit()
1452 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC, in tryInstructionSplit()
1455 (!SplitSubClass && VirtReg.hasSubRanges() && in tryInstructionSplit()
1456 !readsLaneSubset(*MRI, MI, VirtReg, TRI, Use, TII))) { in tryInstructionSplit()
1474 DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS); in tryInstructionSplit()
1567 unsigned RAGreedy::tryLocalSplit(const LiveInterval &VirtReg, in tryLocalSplit() argument
1599 if (Matrix->checkRegMaskInterference(VirtReg)) { in tryLocalSplit()
1645 bool ProgressRequired = ExtraInfo->getStage(VirtReg) >= RS_Split2; in tryLocalSplit()
1664 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg)) in tryLocalSplit()
1760 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in tryLocalSplit()
1769 DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS); in tryLocalSplit()
1798 unsigned RAGreedy::trySplit(const LiveInterval &VirtReg, AllocationOrder &Order, in trySplit() argument
1802 if (ExtraInfo->getStage(VirtReg) >= RS_Spill) in trySplit()
1806 if (LIS->intervalIsInOneMBB(VirtReg)) { in trySplit()
1809 SA->analyze(&VirtReg); in trySplit()
1810 Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs); in trySplit()
1813 return tryInstructionSplit(VirtReg, Order, NewVRegs); in trySplit()
1819 SA->analyze(&VirtReg); in trySplit()
1824 if (ExtraInfo->getStage(VirtReg) < RS_Split2) { in trySplit()
1825 MCRegister PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs); in trySplit()
1831 return tryBlockSplit(VirtReg, Order, NewVRegs); in trySplit()
1868 MCRegister PhysReg, const LiveInterval &VirtReg, in mayRecolorAllInterferences() argument
1870 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg()); in mayRecolorAllInterferences()
1873 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in mayRecolorAllInterferences()
1898 !(hasTiedDef(MRI, VirtReg.reg()) && in mayRecolorAllInterferences()
1954 unsigned RAGreedy::tryLastChanceRecoloring(const LiveInterval &VirtReg, in tryLastChanceRecoloring() argument
1960 if (!TRI->shouldUseLastChanceRecoloringForVirtReg(*MF, VirtReg)) in tryLastChanceRecoloring()
1963 LLVM_DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n'); in tryLastChanceRecoloring()
1968 assert((ExtraInfo->getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) && in tryLastChanceRecoloring()
1985 assert(!FixedRegisters.count(VirtReg.reg())); in tryLastChanceRecoloring()
1986 FixedRegisters.insert(VirtReg.reg()); in tryLastChanceRecoloring()
1991 LLVM_DEBUG(dbgs() << "Try to assign: " << VirtReg << " to " in tryLastChanceRecoloring()
1997 if (Matrix->checkInterference(VirtReg, PhysReg) > in tryLastChanceRecoloring()
2007 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates, in tryLastChanceRecoloring()
2033 Matrix->assign(VirtReg, PhysReg); in tryLastChanceRecoloring()
2046 Matrix->unassign(VirtReg); in tryLastChanceRecoloring()
2050 LLVM_DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to " in tryLastChanceRecoloring()
2055 Matrix->unassign(VirtReg); in tryLastChanceRecoloring()
2142 MCRegister RAGreedy::selectOrSplit(const LiveInterval &VirtReg, in selectOrSplit() argument
2149 selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters, RecolorStack); in selectOrSplit()
2175 const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg, in tryAssignCSRFirstTime() argument
2177 if (ExtraInfo->getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) { in tryAssignCSRFirstTime()
2180 SA->analyze(&VirtReg); in tryAssignCSRFirstTime()
2189 if (ExtraInfo->getStage(VirtReg) < RS_Split) { in tryAssignCSRFirstTime()
2192 SA->analyze(&VirtReg); in tryAssignCSRFirstTime()
2195 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost, in tryAssignCSRFirstTime()
2202 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs); in tryAssignCSRFirstTime()
2283 void RAGreedy::tryHintRecoloring(const LiveInterval &VirtReg) { in tryHintRecoloring() argument
2290 Register Reg = VirtReg.reg(); in tryHintRecoloring()
2408 MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg, in selectOrSplitImpl() argument
2416 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplitImpl()
2418 tryAssign(VirtReg, Order, NewVRegs, FixedRegisters)) { in selectOrSplitImpl()
2424 MCRegister CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg, in selectOrSplitImpl()
2437 LiveRangeStage Stage = ExtraInfo->getStage(VirtReg); in selectOrSplitImpl()
2439 << ExtraInfo->getCascade(VirtReg.reg()) << '\n'); in selectOrSplitImpl()
2446 tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit, in selectOrSplitImpl()
2448 Register Hint = MRI->getSimpleHint(VirtReg.reg()); in selectOrSplitImpl()
2455 SetOfBrokenHints.insert(&VirtReg); in selectOrSplitImpl()
2465 ExtraInfo->setStage(VirtReg, RS_Split); in selectOrSplitImpl()
2467 NewVRegs.push_back(VirtReg.reg()); in selectOrSplitImpl()
2474 Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters); in selectOrSplitImpl()
2481 if (Stage >= RS_Done || !VirtReg.isSpillable()) { in selectOrSplitImpl()
2482 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters, in selectOrSplitImpl()
2488 TRI->shouldUseDeferredSpillingForVirtReg(*MF, VirtReg)) && in selectOrSplitImpl()
2489 ExtraInfo->getStage(VirtReg) < RS_Memory) { in selectOrSplitImpl()
2494 ExtraInfo->setStage(VirtReg, RS_Memory); in selectOrSplitImpl()
2496 NewVRegs.push_back(VirtReg.reg()); in selectOrSplitImpl()
2500 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); in selectOrSplitImpl()
2507 DebugVars->splitRegister(VirtReg.reg(), LRE.regs(), *LIS); in selectOrSplitImpl()