Lines Matching refs:VirtReg
202 Register VirtReg; ///< Virtual register number. member
208 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
211 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
351 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg() argument
352 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
355 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { in findLiveVirtReg()
356 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
363 void assignDanglingDebugValues(MachineInstr &Def, Register VirtReg,
366 Register VirtReg);
367 bool defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
369 bool useVirtReg(MachineInstr &MI, MachineOperand &MO, Register VirtReg);
378 Register traceCopies(Register VirtReg) const;
382 int getStackSpaceFor(Register VirtReg);
383 void spill(MachineBasicBlock::iterator Before, Register VirtReg,
385 void reload(MachineBasicBlock::iterator Before, Register VirtReg,
388 bool mayLiveOut(Register VirtReg);
389 bool mayLiveIn(Register VirtReg);
464 int RegAllocFastImpl::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor() argument
466 int SS = StackSlotForVirtReg[VirtReg]; in getStackSpaceFor()
472 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
478 StackSlotForVirtReg[VirtReg] = FrameIdx; in getStackSpaceFor()
492 bool RegAllocFastImpl::mayLiveOut(Register VirtReg) { in mayLiveOut() argument
493 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) { in mayLiveOut()
504 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveOut()
506 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
514 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
523 for (const MachineInstr &UseInst : MRI->use_nodbg_instructions(VirtReg)) { in mayLiveOut()
525 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
535 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
545 bool RegAllocFastImpl::mayLiveIn(Register VirtReg) { in mayLiveIn() argument
546 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) in mayLiveIn()
552 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveIn()
554 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveIn()
565 Register VirtReg, MCPhysReg AssignedReg, bool Kill, in spill() argument
567 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " in " in spill()
569 int FI = getStackSpaceFor(VirtReg); in spill()
572 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
574 VirtReg); in spill()
582 SmallVectorImpl<MachineOperand *> &LRIDbgOperands = LiveDbgValueMap[VirtReg]; in spill()
626 Register VirtReg, MCPhysReg PhysReg) { in reload() argument
627 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " in reload()
629 int FI = getStackSpaceFor(VirtReg); in reload()
630 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in reload()
631 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg); in reload()
699 reload(MBB.begin(), LR.VirtReg, PhysReg); in reloadAtBegin()
701 reload(InsertBefore, LR.VirtReg, PhysReg); in reloadAtBegin()
730 switch (unsigned VirtReg = RegUnitStates[Unit]) { in displacePhysReg() local
732 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); in displacePhysReg()
736 reload(ReloadBefore, VirtReg, LRI->PhysReg); in displacePhysReg()
759 switch (unsigned VirtReg = RegUnitStates[FirstUnit]) { in freePhysReg() local
768 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); in freePhysReg()
770 LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n'); in freePhysReg()
784 switch (unsigned VirtReg = RegUnitStates[Unit]) { in calcSpillCost() local
792 bool SureSpill = StackSlotForVirtReg[VirtReg] != -1 || in calcSpillCost()
793 findLiveVirtReg(VirtReg)->LiveOut; in calcSpillCost()
802 Register VirtReg, in assignDanglingDebugValues() argument
804 auto UDBGValIter = DanglingDbgValues.find(VirtReg); in assignDanglingDebugValues()
811 if (!DbgValue->hasDebugOperandForReg(VirtReg)) in assignDanglingDebugValues()
827 for (MachineOperand &MO : DbgValue->getDebugOperandsForReg(VirtReg)) { in assignDanglingDebugValues()
841 Register VirtReg = LR.VirtReg; in assignVirtToPhysReg() local
842 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to " in assignVirtToPhysReg()
847 setPhysRegState(PhysReg, VirtReg); in assignVirtToPhysReg()
849 assignDanglingDebugValues(AtMI, VirtReg, PhysReg); in assignVirtToPhysReg()
873 Register RegAllocFastImpl::traceCopies(Register VirtReg) const { in traceCopies()
876 for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) { in traceCopies()
893 const Register VirtReg = LR.VirtReg; in allocVirtReg() local
896 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtReg()
897 LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg) in allocVirtReg()
919 Register Hint1 = traceCopies(VirtReg); in allocVirtReg()
982 Register VirtReg = MO.getReg(); in allocVirtRegUndef() local
983 assert(VirtReg.isVirtual() && "Expected virtreg"); in allocVirtRegUndef()
984 if (!shouldAllocateRegister(VirtReg)) in allocVirtRegUndef()
987 LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg); in allocVirtRegUndef()
992 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtRegUndef()
1012 Register VirtReg) { in defineLiveThroughVirtReg() argument
1013 if (!shouldAllocateRegister(VirtReg)) in defineLiveThroughVirtReg()
1015 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); in defineLiveThroughVirtReg()
1037 return defineVirtReg(MI, OpNum, VirtReg, true); in defineLiveThroughVirtReg()
1048 Register VirtReg, bool LookAtPhysRegUses) { in defineVirtReg() argument
1049 assert(VirtReg.isVirtual() && "Not a virtual register"); in defineVirtReg()
1050 if (!shouldAllocateRegister(VirtReg)) in defineVirtReg()
1055 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); in defineVirtReg()
1058 if (mayLiveOut(VirtReg)) { in defineVirtReg()
1071 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in defineVirtReg()
1080 LLVM_DEBUG(dbgs() << "In def of " << printReg(VirtReg, TRI) in defineVirtReg()
1093 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut); in defineVirtReg()
1098 int FI = StackSlotForVirtReg[VirtReg]; in defineVirtReg()
1099 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in defineVirtReg()
1104 &RC, TRI, VirtReg); in defineVirtReg()
1117 BundleVirtRegsMap[VirtReg] = PhysReg; in defineVirtReg()
1126 Register VirtReg) { in useVirtReg() argument
1127 assert(VirtReg.isVirtual() && "Not a virtual register"); in useVirtReg()
1128 if (!shouldAllocateRegister(VirtReg)) in useVirtReg()
1132 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); in useVirtReg()
1135 if (mayLiveOut(VirtReg)) { in useVirtReg()
1162 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in useVirtReg()
1173 BundleVirtRegsMap[VirtReg] = LRI->PhysReg; in useVirtReg()
1224 switch (unsigned VirtReg = RegUnitStates[Unit]) { in dumpState() local
1233 dbgs() << ' ' << printRegUnit(Unit, TRI) << '=' << printReg(VirtReg); in dumpState()
1234 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg); in dumpState()
1252 Register VirtReg = LR.VirtReg; in dumpState() local
1253 assert(VirtReg.isVirtual() && "Bad map key"); in dumpState()
1258 assert(RegUnitStates[Unit] == VirtReg && "inverse map valid"); in dumpState()