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Searched refs:VR (Results 1 – 25 of 68) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp216 unsigned operator[](unsigned VR) const { in operator []()
217 const_iterator F = find(VR); in operator []()
274 const BitTracker::RegisterCell &lookup(unsigned VR) { in lookup()
275 unsigned RInd = Register(VR).virtRegIndex(); in lookup()
281 CP = CVect[RInd] = &BT.lookup(VR); in lookup()
390 void insert(unsigned VR);
391 void remove(unsigned VR);
443 void OrderedRegisterList::insert(unsigned VR) { in insert() argument
444 iterator L = llvm::lower_bound(Seq, VR, Ord); in insert()
446 Seq.push_back(VR); in insert()
[all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/profile/
H A DInstrProfilingMergeFile.c28 ValueProfRecord *VR = getFirstValueProfRecord(SrcValueProfData); in lprofMergeValueProfData() local
30 VData = getValueProfRecordValueData(VR); in lprofMergeValueProfData()
32 for (S = 0; S < VR->NumValueSites; S++) { in lprofMergeValueProfData()
33 uint8_t NV = VR->SiteCountArray[S]; in lprofMergeValueProfData()
41 VR = getValueProfRecordNext(VR); in lprofMergeValueProfData()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td342 (outs VR:$vd),
357 (outs VR:$vd),
364 (outs VR:$vd),
370 (outs VR:$vd),
377 (outs VR:$vd),
378 (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
384 (outs VR:$vd),
390 (outs VR:$vd),
396 (outs VR:$vd),
404 (outs VR:$vd),
[all …]
H A DRISCVInstrInfoXSf.td108 bits<3> Funct3 = !cond(!eq(TyRs1, VR): 0b000,
131 !if(!eq(TyRs1, VR), VCIXVS2VS1, VCIXVS2));
166 defm SF_VC_V_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, VR, InTyRs2,
183 : RVInstVCCustom2<funct6{5-2}, opv.Value, (outs VR:$rd), (ins VR:$rs1, VR:$rs2),
204 defm XV : CustomSiFiveVCIX<"xv", VCIX_XV, uimm5, VR, GPR>, Sched<[]>;
205 defm IV : CustomSiFiveVCIX<"iv", VCIX_XV, uimm5, VR, simm5>, Sched<[]>;
206 defm VV : CustomSiFiveVCIX<"vv", VCIX_XV, uimm5, VR, VR>, Sched<[]>;
207 defm FV : CustomSiFiveVCIX<"fv", VCIX_XV, uimm5, VR, FPR32>, Sched<[]>;
208 defm XVV : CustomSiFiveVCIX<"xvv", VCIX_XVV, VR, VR, GPR>, Sched<[]>;
209 defm IVV : CustomSiFiveVCIX<"ivv", VCIX_XVV, VR, VR, simm5>, Sched<[]>;
[all …]
H A DRISCVInstrInfoXSfmm.td226 def SF_VTMV_V_T : SFInstTileMoveOp<0b010000, (outs VR:$vd), (ins GPR:$rs1),
230 def SF_VTMV_T_V : SFInstTileMoveOp<0b010111, (outs), (ins GPR:$rs1, VR:$rs2),
250 def SF_MM_F_F : SFInstMatmulF<(outs), (ins TRM2:$rd, VR:$vs2, VR:$vs1),
259 (outs), (ins TRM4:$rd, VR:$vs2, VR:$vs1),
269 (outs), (ins TRM4:$rd, VR:$vs2, VR:$vs1),
H A DRISCVInstrInfoVVLPatterns.td1151 VR:$passthru,
1155 VR:$passthru,
1167 VR:$passthru,
1171 VR:$passthru, vti.RegClass:$rs1,
1181 VR:$passthru,
1184 (instruction_masked VR:$passthru, vti.RegClass:$rs1,
1189 VR:$passthru,
1192 (instruction_masked VR:$passthru, vti.RegClass:$rs1,
1203 VR:$passthru,
1206 (instruction_masked VR:$passthru, vti.RegClass:$rs1,
[all …]
H A DRISCVInstrInfoVSDPatterns.td53 def : Pat<(store (m.Mask VR:$rs2), GPR:$rs1),
54 (store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>;
1167 def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)),
1169 VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
1170 def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)),
1172 VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
1173 def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)),
1175 VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
1177 def : Pat<(mti.Mask (rvv_vnot (and VR:$rs1, VR:$rs2))),
1179 VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>;
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H A DRISCVInstrInfoXTHead.td85 : THInstVdotVV<funct6, opv, (outs VR:$vd_wb),
86 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),
95 : THInstVdotVX<funct6, opv, (outs VR:$vd_wb),
96 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
486 def THVdotV_M1 : LMULInfo<0b000, 8, VR, VR, VR, VR, VR, "M1">;
487 def THVdotV_M2 : LMULInfo<0b001, 16, VRM2, VRM2, VR, VR, VR, "M2">;
488 def THVdotV_M4 : LMULInfo<0b010, 32, VRM4, VRM4, VRM2, VR, VR, "M4">;
489 def THVdotV_M8 : LMULInfo<0b011, 64, VRM8, VRM8, VRM4, VRM2, VR, "M8">;
H A DRISCVInstrInfoXRivos.td122 def RI_VZERO : RVInstV<0b000000, 0b00000, OPCFG, (outs VR:$vd),
125 def RI_VINSERT : CustomRivosVXI<0b010000, OPMVX, (outs VR:$vd_wb),
126 (ins VR:$vd, GPR:$rs1, uimm5:$imm),
130 (ins VR:$vs2, uimm5:$imm),
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dvdev_raidz_math_powerpc_altivec_common.h60 #define VR(X) "%[w"#X"]" macro
401 "vspltisb " VR(16) ",14\n" \
402 "vspltisb " VR(17) ",15\n" \
403 "vaddubm " VR(16) "," VR(17) "," VR(16) "\n" \
404 "vxor " VR(17) "," VR(17) "," VR(17) "\n" \
413 "vcmpgtsb 19," VR(17) "," VR0(r) "\n" \
414 "vcmpgtsb 18," VR(17) "," VR1(r) "\n" \
415 "vcmpgtsb 21," VR(17) "," VR2(r) "\n" \
416 "vcmpgtsb 20," VR(17) "," VR3(r) "\n" \
417 "vand 19,19," VR(16) "\n" \
[all …]
H A Dvdev_raidz_math_aarch64_neon_common.h63 #define VR(X) "%[w"#X"]" macro
402 "eor " VR(17) ".16b," VR(17) ".16b," VR(17) ".16b\n" \
403 "movi " VR(16) ".16b,#0x1d\n" \
412 "cmgt v19.16b," VR(17) ".16b," VR0(r) ".16b\n" \
413 "cmgt v18.16b," VR(17) ".16b," VR1(r) ".16b\n" \
414 "cmgt v21.16b," VR(17) ".16b," VR2(r) ".16b\n" \
415 "cmgt v20.16b," VR(17) ".16b," VR3(r) ".16b\n" \
416 "and v19.16b,v19.16b," VR(16) ".16b\n" \
417 "and v18.16b,v18.16b," VR(16) ".16b\n" \
418 "and v21.16b,v21.16b," VR(16) ".16b\n" \
[all …]
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DMacOSXAPIChecker.cpp94 if (const VarRegion *VR = dyn_cast<VarRegion>(R->getBaseRegion())) { in CheckDispatchOnce() local
95 const VarDecl *VD = VR->getDecl(); in CheckDispatchOnce()
104 if (VR != R) in CheckDispatchOnce()
110 os << VR->getDecl()->getName() << '\''; in CheckDispatchOnce()
H A DMIGChecker.cpp136 const auto *VR = dyn_cast<VarRegion>(MR); in REGISTER_TRAIT_WITH_PROGRAMSTATE() local
137 if (VR && VR->hasMemorySpace<StackArgumentsSpaceRegion>(C.getState()) && in REGISTER_TRAIT_WITH_PROGRAMSTATE()
138 VR->getStackFrame()->inTopFrame()) in REGISTER_TRAIT_WITH_PROGRAMSTATE()
139 return cast<ParmVarDecl>(VR->getDecl()); in REGISTER_TRAIT_WITH_PROGRAMSTATE()
H A DStackAddrEscapeChecker.cpp95 } else if (const auto *VR = dyn_cast<VarRegion>(R)) { in genName() local
96 os << "stack memory associated with local variable '" << VR->getString() in genName()
98 range = VR->getDecl()->getSourceRange(); in genName()
549 const MemRegion *VR = Val.getAsRegion(); in checkEndFunction() local
550 if (!VR) in checkEndFunction()
553 if (checkForDanglingStackVariable(Region, VR)) in checkEndFunction()
561 if (VR) { in checkEndFunction()
562 if (const auto *S = VR->getMemorySpaceAs<StackSpaceRegion>(State); in checkEndFunction()
564 V.emplace_back(Region, VR); in checkEndFunction()
H A DNSErrorChecker.cpp203 if (const VarRegion *VR = R->getAs<VarRegion>()) in parameterTypeFromSVal() local
205 VR->getMemorySpaceAs<StackArgumentsSpaceRegion>(C.getState())) in parameterTypeFromSVal()
207 return VR->getValueType(); in parameterTypeFromSVal()
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-opp-zaius.dts393 /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
394 /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
395 /* CPU0 VR ISL68137 0.8V PMBUS @60h */
396 /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */
397 /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
431 /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */
432 /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */
433 /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */
434 /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
435 /* CPU1 VR ISL68137 0.8V PMBUS @60h */
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DSymbolManager.cpp317 if (const auto *VR = dyn_cast<VarRegion>(MR)) in isLiveRegion() local
318 return isLive(VR, true); in isLiveRegion()
408 bool SymbolReaper::isLive(const VarRegion *VR, bool includeStoreBindings) const{ in isLive() argument
409 const StackFrameContext *VarContext = VR->getStackFrame(); in isLive()
428 if (LCtx->getAnalysis<RelaxedLiveVariables>()->isLive(Loc, VR->getDecl())) in isLive()
435 const_cast<SymbolReaper *>(this)->includedRegionCache[VR]; in isLive()
444 reapedStore.getStoreManager().includedInBindings(store, VR); in isLive()
H A DMemRegion.cpp795 if (auto *VR = dyn_cast<VarRegion>(this->getBaseRegion())) { in sourceRange() local
796 return VR->getDecl()->getSourceRange(); in sourceRange()
1013 if (const auto *VR = dyn_cast<VarRegion>(OrigR)) { in getStackOrCaptureRegionForDeclContext() local
1014 if (VR->getDecl() == VD) in getStackOrCaptureRegionForDeclContext()
1095 if (const auto *VR = dyn_cast_if_present<const VarRegion *>(V)) in getVarRegion() local
1096 return VR; in getVarRegion()
1731 const VarRegion *VR = nullptr; in getCaptureRegions() local
1735 VR = MemMgr.getNonParamVarRegion(VD, this); in getCaptureRegions()
1740 VR = MemMgr.getVarRegion(VD, LC); in getCaptureRegions()
1741 OriginalVR = VR; in getCaptureRegions()
[all …]
H A DBugReporterVisitors.cpp586 const MemRegion *VR = V.getAsRegion(); in findRegionOfInterestInRecord() local
591 if (RegionOfInterest == VR) in findRegionOfInterestInRecord()
600 if (PT.isNull() || PT->isVoidType() || !VR) in findRegionOfInterestInRecord()
605 findRegionOfInterestInRecord(RRD, State, VR, VecF, depth + 1)) in findRegionOfInterestInRecord()
1179 static bool isInitializationOfVar(const ExplodedNode *N, const VarRegion *VR) { in isInitializationOfVar() argument
1188 if (DS->getSingleDecl() != VR->getDecl()) in isInitializationOfVar()
1192 VR->getMemorySpaceAs<StackSpaceRegion>(N->getState()); in isInitializationOfVar()
1199 VR->getDecl()->isStaticLocal() || VR->getDecl()->isLocalExternDecl(); in isInitializationOfVar()
1205 assert(VR->getDecl()->hasLocalStorage()); in isInitializationOfVar()
1306 const auto *VR = cast<VarRegion>(SI.Dest); in showBRParamDiagnostics() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp180 Register VR = in emitPrologue() local
182 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSRI32), VR) in emitPrologue()
186 .addReg(VR) in emitPrologue()
189 Register VR = in emitPrologue() local
191 BuildMI(MBB, MBBI, DL, TII->get(CSKY::MOV16), VR).addReg(SPReg); in emitPrologue()
192 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSRI16), VR) in emitPrologue()
193 .addReg(VR) in emitPrologue()
195 BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSLI16), VR) in emitPrologue()
196 .addReg(VR) in emitPrologue()
198 BuildMI(MBB, MBBI, DL, TII->get(CSKY::MOV16), SPReg).addReg(VR); in emitPrologue()
/freebsd/contrib/llvm-project/llvm/lib/ProfileData/
H A DInstrProf.cpp1241 ValueProfRecord *VR = getFirstValueProfRecord(this); in deserializeTo() local
1243 VR->deserializeTo(Record, SymTab); in deserializeTo()
1244 VR = getValueProfRecordNext(VR); in deserializeTo()
1262 ValueProfRecord *VR = getFirstValueProfRecord(this); in checkIntegrity() local
1264 if (VR->Kind > IPVK_Last) in checkIntegrity()
1267 VR = getValueProfRecordNext(VR); in checkIntegrity()
1268 if ((char *)VR - (char *)this > (ptrdiff_t)TotalSize) in checkIntegrity()
1312 ValueProfRecord *VR = getFirstValueProfRecord(this); in swapBytesToHost() local
1314 VR->swapBytes(Endianness, llvm::endianness::native); in swapBytesToHost()
1315 VR = getValueProfRecordNext(VR); in swapBytesToHost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DREADME_P9.txt57 VR[VRT].word[i] ← EXTS32(VR[VRB].word[i].byte[3])
65 VR[VRT].word[i] ← EXTS32(VR[VRB].word[i].hword[1])
73 VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].byte[7])
81 VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].hword[3])
89 VR[VRT].dword[i] ← EXTS64(VR[VRB].dword[i].word[1])
122 sh ← VR[VRB].byte[i].bit[5:7]
123 VR[VRT].byte[i] ← src.byte[i:i+1].bit[sh:sh+7]
126 VR[VRT].byte[i] is composed of 2 bytes from src.byte[i:i+1]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h328 static bool bind(const MachineRegisterInfo &MRI, BindTy &VR, BindTy &V) {
329 VR = V;
382 Class &VR;
384 bind_ty(Class &V) : VR(V) {}
387 return bind_helper<Class>::bind(MRI, VR, V);
402 static bool match(const MachineRegisterInfo &MRI, BindTy &VR, BindTy &V) {
403 return VR == V;
414 Class &VR;
416 deferred_ty(Class &V) : VR(V) {}
419 return deferred_helper<Class>::match(MRI, VR, V);
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp172 Register VR = MRI.createVirtualRegister(RC); in expandLoadCCond() local
175 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
177 .addReg(VR, RegState::Kill); in expandLoadCCond()
187 Register VR = MRI.createVirtualRegister(RC); in expandStoreCCond() local
190 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
192 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
505 Register VR = MF.getRegInfo().createVirtualRegister(RC); in emitPrologue() local
510 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign); in emitPrologue()
511 BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR); in emitPrologue()
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DScalarEvolutionPatternMatch.h72 Class *&VR; member
74 bind_ty(Class *&V) : VR(V) {} in bind_ty()
78 VR = CV; in match()

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