| /freebsd/contrib/llvm-project/llvm/lib/DWARFCFIChecker/ |
| H A D | Registers.h | 56 for (auto SuperReg : MCRI->superregs(Reg)) in getSuperReg() local
57 if (isSuperReg(MCRI, SuperReg)) in getSuperReg()
58 return SuperReg; in getSuperReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 540 MCRegister SuperReg, unsigned AntiDepGroupIndex, in FindSuitableFreeRegisters() argument
581 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
582 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
597 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) in FindSuitableFreeRegisters()
611 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
633 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
643 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
646 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
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| H A D | AggressiveAntiDepBreaker.h | 180 bool FindSuitableFreeRegisters(MCRegister SuperReg,
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| H A D | CriticalAntiDepBreaker.cpp | 244 for (MCPhysReg SuperReg : TRI->superregs(Reg)) { in PrescanInstruction() local
245 KeepRegs.set(SuperReg); in PrescanInstruction()
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| H A D | PrologEpilogInserter.cpp | 473 for (const MCPhysReg &SuperReg : RegInfo->superregs(Reg)) { in assignCalleeSavedSpillSlots() local
476 if (SavedRegs.test(SuperReg) && CSMask.test(SuperReg)) { in assignCalleeSavedSpillSlots()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 86 Register SuperReg; member
127 : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()), in SGPRSpillBuilder()
131 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); in SGPRSpillBuilder()
145 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in SGPRSpillBuilder()
146 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
147 SuperReg != AMDGPU::EXEC && "exec should never spill"); in SGPRSpillBuilder()
208 RS->setRegUsed(SuperReg); in prepare()
2045 assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() && in spillSGPR()
2046 SB.SuperReg != SB.MFI.getFrameOffsetReg())); in spillSGPR()
2061 ? SB.SuperReg in spillSGPR()
[all …]
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| H A D | SIFrameLowering.cpp | 233 Register SuperReg; member in llvm::PrologEpilogSGPRSpillBuilder
255 ? SuperReg in saveToMemory()
256 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToMemory()
276 ? SuperReg in saveToVGPRLane()
277 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToVGPRLane()
288 .addReg(SuperReg) in copyToScratchSGPR()
303 ? SuperReg in restoreFromMemory()
304 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in restoreFromMemory()
323 ? SuperReg in restoreFromVGPRLane()
324 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in restoreFromVGPRLane()
[all …]
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| H A D | SIInstrInfo.h | 111 const MachineOperand &SuperReg,
117 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
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| H A D | SIInstrInfo.cpp | 5902 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
5904 if (!SuperReg.getReg().isVirtual()) in buildExtractSubReg()
5905 return RI.getSubReg(SuperReg.getReg(), SubIdx); in buildExtractSubReg()
5911 unsigned NewSubIdx = RI.composeSubRegIndices(SuperReg.getSubReg(), SubIdx); in buildExtractSubReg()
5913 .addReg(SuperReg.getReg(), 0, NewSubIdx); in buildExtractSubReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1741 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1744 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1777 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1779 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1783 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1887 SDValue SuperReg = SDValue(WhilePair, 0); in SelectPExtPair() local
1891 AArch64::psub0 + I, DL, VT, SuperReg)); in SelectPExtPair()
1903 SDValue SuperReg = SDValue(WhilePair, 0); in SelectWhilePair() local
1907 AArch64::psub0 + I, DL, VT, SuperReg)); in SelectWhilePair()
1919 SDValue SuperReg = SDValue(Intrinsic, 0); in SelectCVTIntrinsic() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2234 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
2241 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2483 SDValue SuperReg; in SelectVLDSTLane() local
2488 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2490 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2497 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2499 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2501 Ops.push_back(SuperReg); in SelectVLDSTLane()
2517 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2524 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1686 MCRegister SuperReg = in copyPhysReg() local
1689 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
1692 DestReg = SuperReg; in copyPhysReg()
1695 MCRegister SuperReg = in copyPhysReg() local
1698 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
1701 SrcReg = SuperReg; in copyPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 7174 Register SuperReg = getX86SubSuperRegister(Reg, 64); in breakPartialRegDependency() local
7176 if (!MI.definesRegister(SuperReg, /*TRI=*/nullptr)) in breakPartialRegDependency()
7177 BuildMI.addReg(SuperReg, RegState::ImplicitDefine); in breakPartialRegDependency()
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