| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | PointerSubChecker.cpp | 67 const MemRegion *SuperReg = ElemReg->getSuperRegion(); in checkArrayBounds() local
70 if (SuperReg == Reg) { in checkArrayBounds()
78 getDynamicElementCount(State, SuperReg, SVB, ElemReg->getElementType()); in checkArrayBounds()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 80 Register SuperReg; member
121 : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()), in SGPRSpillBuilder()
125 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); in SGPRSpillBuilder()
139 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in SGPRSpillBuilder()
140 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
141 SuperReg != AMDGPU::EXEC && "exec should never spill"); in SGPRSpillBuilder()
202 RS->setRegUsed(SuperReg); in prepare()
1773 assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() && in spillSGPR()
1774 SB.SuperReg != SB.MFI.getFrameOffsetReg())); in spillSGPR()
1784 ? SB.SuperReg in spillSGPR()
[all …]
|
| H A D | SIFrameLowering.cpp | 233 Register SuperReg; member in llvm::PrologEpilogSGPRSpillBuilder
255 ? SuperReg in saveToMemory()
256 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToMemory()
276 ? SuperReg in saveToVGPRLane()
277 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in saveToVGPRLane()
288 .addReg(SuperReg) in copyToScratchSGPR()
303 ? SuperReg in restoreFromMemory()
304 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in restoreFromMemory()
322 ? SuperReg in restoreFromVGPRLane()
323 : Register(TRI.getSubReg(SuperReg, SplitParts[I])); in restoreFromVGPRLane()
[all …]
|
| H A D | SIInstrInfo.h | 109 const MachineOperand &SuperReg,
115 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
|
| H A D | SIInstrInfo.cpp | 5653 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
5659 unsigned NewSubIdx = RI.composeSubRegIndices(SuperReg.getSubReg(), SubIdx); in buildExtractSubReg()
5661 .addReg(SuperReg.getReg(), 0, NewSubIdx); in buildExtractSubReg()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 536 unsigned SuperReg, unsigned AntiDepGroupIndex, RenameOrderType &RenameOrder, in FindSuitableFreeRegisters() argument
577 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
578 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
593 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) in FindSuitableFreeRegisters()
607 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
629 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
639 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
642 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
|
| H A D | CriticalAntiDepBreaker.cpp | 243 for (MCPhysReg SuperReg : TRI->superregs(Reg)) { in PrescanInstruction() local
244 KeepRegs.set(SuperReg); in PrescanInstruction()
|
| H A D | PrologEpilogInserter.cpp | 447 for (const MCPhysReg &SuperReg : RegInfo->superregs(Reg)) { in assignCalleeSavedSpillSlots() local
450 if (SavedRegs.test(SuperReg) && CSMask.test(SuperReg)) { in assignCalleeSavedSpillSlots()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1690 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1693 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1726 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1728 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1732 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1836 SDValue SuperReg = SDValue(WhilePair, 0); in SelectPExtPair() local
1840 AArch64::psub0 + I, DL, VT, SuperReg)); in SelectPExtPair()
1852 SDValue SuperReg = SDValue(WhilePair, 0); in SelectWhilePair() local
1856 AArch64::psub0 + I, DL, VT, SuperReg)); in SelectWhilePair()
1868 SDValue SuperReg = SDValue(Intrinsic, 0); in SelectCVTIntrinsic() local
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2243 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
2250 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2492 SDValue SuperReg; in SelectVLDSTLane() local
2497 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2499 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2506 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2508 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2510 Ops.push_back(SuperReg); in SelectVLDSTLane()
2526 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2533 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 368 SDValue SuperReg = SDValue(Load, 0); in selectVLSEG() local
372 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEG()
409 SDValue SuperReg = SDValue(Load, 0); in selectVLSEGFF() local
413 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLSEGFF()
461 SDValue SuperReg = SDValue(Load, 0); in selectVLXSEG() local
465 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg)); in selectVLXSEG()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1687 MCRegister SuperReg = in copyPhysReg() local
1690 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
1693 DestReg = SuperReg; in copyPhysReg()
1696 MCRegister SuperReg = in copyPhysReg() local
1699 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
1702 SrcReg = SuperReg; in copyPhysReg()
|