80   Register SuperReg;  member
121       : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()),  in SGPRSpillBuilder()
125     const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg);  in SGPRSpillBuilder()
139     assert(SuperReg != AMDGPU::M0 && "m0 should never spill");  in SGPRSpillBuilder()
140     assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI &&  in SGPRSpillBuilder()
141            SuperReg != AMDGPU::EXEC && "exec should never spill");  in SGPRSpillBuilder()
202     RS->setRegUsed(SuperReg);  in prepare()
1773   assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() &&  in spillSGPR()
1774                          SB.SuperReg != SB.MFI.getFrameOffsetReg()));  in spillSGPR()
1784               ? SB.SuperReg  in spillSGPR()
1785               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillSGPR()
1810         MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in spillSGPR()
1814         MIB.addReg(SB.SuperReg, getKillRegState(UseKill) | RegState::Implicit);  in spillSGPR()
1838                 ? SB.SuperReg  in spillSGPR()
1839                 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillSGPR()
1863           WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);  in spillSGPR()
1878     LIS->removeAllRegUnitsForPhysReg(SB.SuperReg);  in spillSGPR()
1900               ? SB.SuperReg  in restoreSGPR()
1901               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in restoreSGPR()
1909         MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in restoreSGPR()
1933                 ? SB.SuperReg  in restoreSGPR()
1934                 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in restoreSGPR()
1942           MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in restoreSGPR()
1958     LIS->removeAllRegUnitsForPhysReg(SB.SuperReg);  in restoreSGPR()
1980               ? SB.SuperReg  in spillEmergencySGPR()
1981               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillEmergencySGPR()
1997         WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState);  in spillEmergencySGPR()
2015               ? SB.SuperReg  in spillEmergencySGPR()
2016               : Register(getSubReg(SB.SuperReg, SB.SplitParts[i]));  in spillEmergencySGPR()
2023         MIB.addReg(SB.SuperReg, RegState::ImplicitDefine);  in spillEmergencySGPR()