| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsOptionRecord.cpp | 74 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
75 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg); in SetPhysRegUsed()
78 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
80 else if (COP0RegClass->contains(SubReg)) in SetPhysRegUsed()
83 else if (FGR32RegClass->contains(SubReg) || in SetPhysRegUsed()
84 FGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
85 AFGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
86 MSA128BRegClass->contains(SubReg)) in SetPhysRegUsed()
88 else if (COP2RegClass->contains(SubReg)) in SetPhysRegUsed()
90 else if (COP3RegClass->contains(SubReg)) in SetPhysRegUsed()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveVariables.cpp | 223 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in FindLastPartialDef() local
224 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
229 LastDefReg = SubReg; in FindLastPartialDef()
272 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegUse() local
273 if (Processed.count(SubReg)) in HandlePhysRegUse()
275 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
279 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
282 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
283 Processed.insert_range(TRI->subregs(SubReg)); in HandlePhysRegUse()
293 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in HandlePhysRegUse() local
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| H A D | LiveIntervalCalc.cpp | 57 unsigned SubReg = MO.getSubReg(); in calculate() local
58 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
59 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
157 unsigned SubReg = MO.getSubReg(); in extendToUses() local
158 if (SubReg != 0) { in extendToUses()
159 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
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| H A D | PeepholeOptimizer.cpp | 408 Src.SubReg = MOInsertedReg.getSubReg(); in getNextRewritableSource()
412 Dst.SubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm(); in getNextRewritableSource()
619 ValueTrackerResult(Register Reg, unsigned SubReg) { addSource(Reg, SubReg); } in ValueTrackerResult() argument
651 return RegSrcs[Idx].SubReg; in getSrcSubReg()
1018 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII); in findNextSource()
1071 CurSrcPair.SubReg)) in findNextSource()
1076 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
1102 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
1110 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1133 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
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| H A D | DetectDeadLanes.cpp | 92 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
93 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
343 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
366 if (SubReg == 0) in determineInitialUsedLanes()
369 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
426 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
427 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
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| H A D | LiveIntervals.cpp | 600 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
601 if (SubReg != 0) { in shrinkToUses()
602 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
827 unsigned SubReg = MO.getSubReg(); in addKillFlags() local
828 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in addKillFlags()
1077 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1078 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1094 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1095 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1511 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
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| H A D | LiveRangeEdit.cpp | 140 unsigned SubReg = MO.getSubReg(); in allUsesAvailableAt() local
141 LaneBitmask LM = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in allUsesAvailableAt()
269 unsigned SubReg = MO.getSubReg(); in useIsKill() local
270 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in useIsKill()
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| H A D | VirtRegMap.cpp | 221 const LiveInterval &LI, const MachineBasicBlock &MBB, unsigned SubReg,
609 const LiveInterval &LI, const MachineBasicBlock &MBB, unsigned SubReg, in liveOutUndefPhiLanesForUndefSubregDef() argument
611 LaneBitmask UndefMask = ~TRI->getSubRegIndexLaneMask(SubReg); in liveOutUndefPhiLanesForUndefSubregDef()
667 unsigned SubReg = MO.getSubReg(); in rewrite() local
668 if (SubReg != 0) { in rewrite()
697 liveOutUndefPhiLanesForUndefSubregDef(LI, *MBBI, SubReg, in rewrite()
732 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewrite()
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| H A D | MachineInstrBundle.cpp | 298 unsigned SubReg = MO.getSubReg(); in AnalyzeVirtRegLanesInBundle() local
299 if (SubReg == 0 && MO.isUse() && !MO.isUndef()) in AnalyzeVirtRegLanesInBundle()
302 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); in AnalyzeVirtRegLanesInBundle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 102 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
104 if (SubReg) in isGPR64()
111 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
115 SubReg == 0) || in isFPR64()
117 SubReg == AArch64::dsub); in isFPR64()
119 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
120 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
127 unsigned &SubReg) { in getSrcFromCopy() argument
128 SubReg = 0; in getSrcFromCopy()
136 SubReg = AArch64::dsub; in getSrcFromCopy()
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| H A D | SMEPeepholeOpt.cpp | 262 MCRegister SubReg = MCRegister::NoRegister; in visitRegSequence() local
272 if (SubReg == MCRegister::NoRegister) in visitRegSequence()
273 SubReg = OpSubReg; in visitRegSequence()
276 if (!CopySrcOp || !CopySrcOp->isReg() || OpSubReg != SubReg || in visitRegSequence()
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| H A D | AArch64RegisterInfo.cpp | 364 for (MCPhysReg SubReg : in UpdateCustomCallPreservedMask() local
368 UpdatedMask[SubReg / 32] |= 1u << (SubReg % 32); in UpdateCustomCallPreservedMask()
477 for (MCPhysReg SubReg : subregs_inclusive(AArch64::ZA)) in getStrictlyReservedRegs() local
478 Reserved.set(SubReg); in getStrictlyReservedRegs()
485 for (MCSubRegIterator SubReg(AArch64::ZT0, this, /*self=*/true); in getStrictlyReservedRegs() local
486 SubReg.isValid(); ++SubReg) in getStrictlyReservedRegs()
487 Reserved.set(*SubReg); in getStrictlyReservedRegs()
1320 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce() argument
1355 if (MI->isCopy() && SubReg != DstSubReg && in shouldCoalesce()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 96 unsigned shiftSubReg(unsigned SubReg, unsigned RShift) const;
167 unsigned GCNRewritePartialRegUsesImpl::shiftSubReg(unsigned SubReg, in shiftSubReg() argument
169 unsigned Offset = TRI->getSubRegIdxOffset(SubReg) - RShift; in shiftSubReg()
170 return getSubReg(Offset, TRI->getSubRegIdxSize(SubReg)); in shiftSubReg()
285 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
286 unsigned SubRegOffset = TRI->getSubRegIdxOffset(SubReg); in getMinSizeReg()
287 unsigned SubRegEnd = SubRegOffset + TRI->getSubRegIdxSize(SubReg); in getMinSizeReg()
297 CoverSubreg = SubReg; in getMinSizeReg()
308 for (auto [SubReg, SRI] : SubRegs) in getMinSizeReg()
309 MaxAlign = std::max(MaxAlign, TRI->getSubRegAlignmentNumBits(RC, SubReg)); in getMinSizeReg()
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| H A D | SIRegisterInfo.h | 347 unsigned SubReg,
401 MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
423 unsigned getChannelFromSubReg(unsigned SubReg) const { in getChannelFromSubReg() argument
424 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0; in getChannelFromSubReg()
428 unsigned getNumChannelsFromSubReg(unsigned SubReg) const { in getNumChannelsFromSubReg() argument
429 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg)); in getNumChannelsFromSubReg()
486 unsigned SubReg) const;
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| H A D | SIShrinkInstructions.cpp | 50 Register Reg, unsigned SubReg) const;
52 unsigned SubReg) const;
54 unsigned SubReg) const;
609 unsigned SubReg) const { in instAccessReg()
618 LaneBitmask Overlap = TRI->getSubRegIndexLaneMask(SubReg) & in instAccessReg()
628 unsigned SubReg) const { in instReadsReg()
629 return instAccessReg(MI->uses(), Reg, SubReg); in instReadsReg()
633 unsigned SubReg) const { in instModifiesReg()
634 return instAccessReg(MI->defs(), Reg, SubReg); in instModifiesReg()
789 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
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| H A D | SIPreAllocateWWMRegs.cpp | 137 const unsigned SubReg = MO.getSubReg(); in rewriteRegs() local
138 if (SubReg != 0) { in rewriteRegs()
139 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
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| H A D | SIRegisterInfo.cpp | 1787 Register SubReg = e == 1 in buildSpillLoadStore() local
1850 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1856 unsigned FinalReg = SubReg; in buildSpillLoadStore()
1869 .addReg(SubReg, getKillRegState(IsKill)); in buildSpillLoadStore()
1876 SubReg = TmpIntermediateVGPR; in buildSpillLoadStore()
1892 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)); in buildSpillLoadStore()
1962 MI->readsRegister(SubReg, this)) { in buildSpillLoadStore()
1963 MIB.addReg(SubReg, RegState::Implicit); in buildSpillLoadStore()
2059 Register SubReg = in spillSGPR() local
2074 .addReg(SubReg, getKillRegState(UseKill)) in spillSGPR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenPredicate.cpp | 57 return OS << printReg(PR.Reg.Reg, &PR.TRI, PR.Reg.SubReg); in operator <<()
201 LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.Reg, TRI, Reg.SubReg) in processPredicateGPR()
207 LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.Reg, TRI, Reg.SubReg) in processPredicateGPR()
252 .addReg(Reg.Reg, 0, Reg.SubReg); in getPredRegFor()
355 if (Reg.SubReg && Reg.SubReg != Hexagon::isub_lo) in convertToPredForm()
405 MIB.addReg(Pred.Reg, 0, Pred.SubReg); in convertToPredForm()
414 .addReg(NewPR.Reg, 0, NewPR.SubReg); in convertToPredForm()
459 assert(!DR.SubReg && !SR.SubReg && "Unexpected subregister"); in eliminatePredCopies()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 299 for (const auto &[SRI, SubReg] : Map) in computeSubRegs()
300 if (Orphans.erase(SubReg)) in computeSubRegs()
301 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SRI)] = SubReg; in computeSubRegs()
305 for (auto &[SRI, SubReg] : SubRegs) { in computeSubRegs()
306 if (SubReg == this) { in computeSubRegs()
320 SubReg2Idx.try_emplace(SubReg, SRI).first; in computeSubRegs()
328 SubReg->getName() + " available as " + in computeSubRegs()
412 for (auto [SRI, SubReg] : SubRegs) in computeSecondarySubRegs()
413 SubRegQueue.emplace(SRI, SubReg); in computeSecondarySubRegs()
419 auto [SubRegIdx, SubReg] = SubRegQueue.front(); in computeSecondarySubRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 131 MCRegister SubReg) const { in getSubRegIndex()
132 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
137 if (Sub == SubReg) in getSubRegIndex()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 101 unsigned SubReg = 0) const {
111 SubReg,
120 unsigned SubReg = 0) const {
121 return addReg(RegNo, Flags | RegState::Define, SubReg);
127 unsigned SubReg = 0) const {
130 return addReg(RegNo, Flags, SubReg);
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| H A D | LivePhysRegs.h | 86 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in addReg() local
87 LiveRegs.insert(SubReg); in addReg()
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| H A D | TargetInstrInfo.h | 528 unsigned SubReg; member
530 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
531 : Reg(Reg), SubReg(SubReg) {} in Reg()
534 return Reg == P.Reg && SubReg == P.SubReg;
547 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0,
549 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
2375 std::make_pair(Val.Reg, Val.SubReg));
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| H A D | TargetRegisterInfo.h | 1169 unsigned SubReg, in shouldCoalesce() argument
1270 unsigned SubReg = 0; variable
1290 unsigned getSubReg() const { return SubReg; } in getSubReg()
1301 SubReg = *Idx++;
1302 if (!SubReg)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.cpp | 389 unsigned SubReg = RI.getSubReg(Reg, M68k::MxSubRegIndex8Lo); in ExpandMOVI() local
390 assert(SubReg && "No viable SUB register available"); in ExpandMOVI()
393 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::NOT8d), SubReg).addReg(SubReg); in ExpandMOVI()
418 unsigned SubReg = RI.getSubReg(Reg, M68k::MxSubRegIndex16Lo); in ExpandMOVI() local
419 assert(SubReg && "No viable SUB register available"); in ExpandMOVI()
422 MIB->getOperand(0).setReg(SubReg); in ExpandMOVI()
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