| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsOptionRecord.cpp | 74 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
75 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg); in SetPhysRegUsed()
78 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
80 else if (COP0RegClass->contains(SubReg)) in SetPhysRegUsed()
83 else if (FGR32RegClass->contains(SubReg) || in SetPhysRegUsed()
84 FGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
85 AFGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
86 MSA128BRegClass->contains(SubReg)) in SetPhysRegUsed()
88 else if (COP2RegClass->contains(SubReg)) in SetPhysRegUsed()
90 else if (COP3RegClass->contains(SubReg)) in SetPhysRegUsed()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 86 unsigned SubReg = AMDGPU::NoSubRegister; member
132 unsigned shiftSubReg(unsigned SubReg, unsigned RShift) const;
180 unsigned GCNRewritePartialRegUses::shiftSubReg(unsigned SubReg, in shiftSubReg() argument
182 unsigned Offset = TRI->getSubRegIdxOffset(SubReg) - RShift; in shiftSubReg()
183 return getSubReg(Offset, TRI->getSubRegIdxSize(SubReg)); in shiftSubReg()
283 for (auto [SubReg, SRI] : SubRegs) in getRegClassWithShiftedSubregs()
285 assert(MinRC == TRI->getSubClassWithSubReg(MinRC, SRI.SubReg)); in getRegClassWithShiftedSubregs()
299 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
300 unsigned SubRegOffset = TRI->getSubRegIdxOffset(SubReg); in getMinSizeReg()
301 unsigned SubRegEnd = SubRegOffset + TRI->getSubRegIdxSize(SubReg); in getMinSizeReg()
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| H A D | SIRegisterInfo.h | 317 unsigned SubReg,
366 MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
387 // \returns a DWORD offset of a \p SubReg in getNumChannelsFromSubReg() argument
388 unsigned getChannelFromSubReg(unsigned SubReg) const { in getNumChannelsFromSubReg()
389 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0; in getNumChannelsFromSubReg()
392 // \returns a DWORD size of a \p SubReg
393 unsigned getNumChannelsFromSubReg(unsigned SubReg) const {
394 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg));
448 // Return alignment of a SubReg relativ
382 getChannelFromSubReg(unsigned SubReg) getChannelFromSubReg() argument
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| H A D | SIShrinkInstructions.cpp | 55 Register Reg, unsigned SubReg) const;
57 unsigned SubReg) const;
59 unsigned SubReg) const;
581 unsigned SubReg) const { in instAccessReg()
590 LaneBitmask Overlap = TRI->getSubRegIndexLaneMask(SubReg) & in instAccessReg()
600 unsigned SubReg) const { in instReadsReg()
601 return instAccessReg(MI->uses(), Reg, SubReg); in instReadsReg()
605 unsigned SubReg) const { in instModifiesReg()
606 return instAccessReg(MI->defs(), Reg, SubReg); in instModifiesReg()
742 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
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| H A D | SIPreAllocateWWMRegs.cpp | 133 const unsigned SubReg = MO.getSubReg(); in rewriteRegs() local
134 if (SubReg != 0) { in rewriteRegs()
135 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
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| H A D | SIRegisterInfo.cpp | 1542 Register SubReg = e == 1 in buildSpillLoadStore() local
1605 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1611 unsigned FinalReg = SubReg; in buildSpillLoadStore()
1624 .addReg(SubReg, getKillRegState(IsKill)); in buildSpillLoadStore()
1629 SubReg = TmpIntermediateVGPR; in buildSpillLoadStore()
1645 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)); in buildSpillLoadStore()
1713 MI->readsRegister(SubReg, this)) { in buildSpillLoadStore()
1714 MIB.addReg(SubReg, RegState::Implicit); in buildSpillLoadStore()
1782 Register SubReg = in spillSGPR() local
1797 .addReg(SubReg, getKillRegState(UseKill)) in spillSGPR()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveVariables.cpp | 224 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in FindLastPartialDef() local
225 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
230 LastDefReg = SubReg; in FindLastPartialDef()
245 for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg)) in FindLastPartialDef() local
246 PartDefRegs.insert(SubReg); in FindLastPartialDef()
275 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in HandlePhysRegUse() local
276 if (Processed.count(SubReg)) in HandlePhysRegUse()
278 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
282 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
285 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
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| H A D | LiveIntervalCalc.cpp | 58 unsigned SubReg = MO.getSubReg(); in calculate()
59 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate() local
60 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
158 unsigned SubReg = MO.getSubReg(); in extendToUses()
159 if (SubReg != 0) { in extendToUses() local
160 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
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| H A D | PeepholeOptimizer.cpp | 340 ValueTrackerResult(Register Reg, unsigned SubReg) { in ValueTrackerResult() argument
341 addSource(Reg, SubReg); in ValueTrackerResult()
376 return RegSrcs[Idx].SubReg; in getSrcSubReg()
744 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII); in findNextSource()
794 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
795 CurSrcPair.SubReg)) in findNextSource()
800 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
826 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
834 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1116 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
[all …]
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| H A D | MachineInstrBundle.cpp | 199 for (MCPhysReg SubReg : TRI->subregs(Reg)) { in finalizeBundle() local
200 if (LocalDefSet.insert(SubReg).second) in finalizeBundle()
201 LocalDefs.push_back(SubReg); in finalizeBundle()
318 unsigned SubReg = MO.getSubReg(); in AnalyzeVirtRegLanesInBundle() local
319 if (SubReg == 0 && MO.isUse() && !MO.isUndef()) in AnalyzeVirtRegLanesInBundle()
322 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); in AnalyzeVirtRegLanesInBundle()
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| H A D | DetectDeadLanes.cpp | 92 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
93 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
343 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
366 if (SubReg == 0) in determineInitialUsedLanes()
369 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
419 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
420 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
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| H A D | LiveIntervals.cpp | 584 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
585 if (SubReg != 0) { in shrinkToUses()
586 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
802 unsigned SubReg = MO.getSubReg(); in addKillFlags() local
803 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in addKillFlags()
1044 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1045 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1061 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1062 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1475 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
[all …]
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| H A D | LiveRangeEdit.cpp | 140 unsigned SubReg = MO.getSubReg(); in allUsesAvailableAt() local
141 LaneBitmask LM = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in allUsesAvailableAt()
273 unsigned SubReg = MO.getSubReg(); in useIsKill() local
274 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in useIsKill()
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| H A D | CriticalAntiDepBreaker.cpp | 216 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in PrescanInstruction() local
217 KeepRegs.set(SubReg); in PrescanInstruction()
240 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) { in PrescanInstruction() local
241 KeepRegs.set(SubReg); in PrescanInstruction()
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| H A D | LiveDebugVariables.cpp | 543 unsigned SubReg; /// Qualifiying subregister for Reg. member
1282 unsigned SubReg = Position.SubReg; in runOnMachineFunction() local
1284 PHIValPos VP = {SI, Reg, SubReg}; in runOnMachineFunction()
1839 unsigned SubReg = It.second.SubReg; in emitDebugValues() local
1845 if (SubReg != 0) in emitDebugValues()
1846 PhysReg = TRI->getSubReg(PhysReg, SubReg); in emitDebugValues()
1858 if (SubReg) in emitDebugValues()
1859 regSizeInBits = TRI->getSubRegIdxSize(SubReg); in emitDebugValues()
1865 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
1880 dbgs() << "DBG_PHI for Vreg " << Reg << " subreg " << SubReg << in emitDebugValues()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
106 if (SubReg) in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
117 SubReg == 0) || in isFPR64()
119 SubReg == AArch64::dsub); in isFPR64()
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy() argument
130 SubReg = 0; in getSrcFromCopy()
138 SubReg = AArch64::dsub; in getSrcFromCopy()
[all …]
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| H A D | AArch64RegisterInfo.cpp | 355 for (MCPhysReg SubReg : in UpdateCustomCallPreservedMask() local
359 UpdatedMask[SubReg / 32] |= 1u << (SubReg % 32); in UpdateCustomCallPreservedMask()
468 for (MCPhysReg SubReg : subregs_inclusive(AArch64::ZA)) in getStrictlyReservedRegs() local
469 Reserved.set(SubReg); in getStrictlyReservedRegs()
476 for (MCSubRegIterator SubReg(AArch64::ZT0, this, /*self=*/true); in getStrictlyReservedRegs() local
477 SubReg.isValid(); ++SubReg) in getStrictlyReservedRegs()
478 Reserved.set(*SubReg); in getStrictlyReservedRegs()
1067 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce() argument
1102 if (MI->isCopy() && SubReg != DstSubReg && in shouldCoalesce()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 266 for (const auto &SubReg : SubRegs) { in inheritRegUnits() local
267 CodeGenRegister *SR = SubReg.second; in inheritRegUnits()
361 for (const auto &SubReg : Map) in computeSubRegs() local
362 if (Orphans.erase(SubReg.second)) in computeSubRegs()
363 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = in computeSubRegs()
364 SubReg.second; in computeSubRegs()
368 for (const auto &SubReg : SubRegs) { in computeSubRegs() local
369 if (SubReg.second == this) { in computeSubRegs()
379 SubReg.first->AllSuperRegsCovered = false; in computeSubRegs()
383 SubReg2Idx.insert(std::pair(SubReg.second, SubReg.first)).first; in computeSubRegs()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 131 MCRegister SubReg) const { in getSubRegIndex()
132 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
137 if (Sub == SubReg) in getSubRegIndex()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 505 unsigned SubReg; member
507 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
508 : Reg(Reg), SubReg(SubReg) {} in Reg()
511 return Reg == P.Reg && SubReg == P.SubReg;
524 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0,
526 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
2301 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
2308 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
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| H A D | MachineInstrBuilder.h | 100 unsigned SubReg = 0) const {
110 SubReg,
119 unsigned SubReg = 0) const {
120 return addReg(RegNo, Flags | RegState::Define, SubReg);
126 unsigned SubReg = 0) const {
129 return addReg(RegNo, Flags, SubReg);
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| H A D | LivePhysRegs.h | 86 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in addReg() local
87 LiveRegs.insert(SubReg); in addReg()
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| H A D | TargetRegisterInfo.h | 1115 unsigned SubReg, in shouldCoalesce() argument
1242 unsigned SubReg = 0; variable
1262 unsigned getSubReg() const { return SubReg; } in getSubReg()
1273 SubReg = *Idx++;
1274 if (!SubReg)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 87 unsigned SubReg; member
89 explicit RegisterSubReg(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {} in RegisterSubReg()
91 : Reg(MO.getReg()), SubReg(MO.getSubReg()) {} in RegisterSubReg()
94 dbgs() << printReg(Reg, TRI, SubReg); in print()
98 return (Reg == R.Reg) && (SubReg == R.SubReg); in operator ==()
639 if (DefR.SubReg) { in visitPHI()
672 << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC in visitPHI()
1084 if (!R.SubReg) { in getCell()
1936 assert(!DefR.SubReg); in evaluate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 550 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs() local
551 Reserved.set(SubReg); in getReservedRegs()
557 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs() local
558 Reserved.set(SubReg); in getReservedRegs()
562 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP)) in getReservedRegs() local
563 Reserved.set(SubReg); in getReservedRegs()
576 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs() local
577 Reserved.set(SubReg); in getReservedRegs()
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