86     unsigned SubReg = AMDGPU::NoSubRegister;  member
132   unsigned shiftSubReg(unsigned SubReg, unsigned RShift) const;
180 unsigned GCNRewritePartialRegUses::shiftSubReg(unsigned SubReg,  in shiftSubReg()  argument
182   unsigned Offset = TRI->getSubRegIdxOffset(SubReg) - RShift;  in shiftSubReg()
183   return getSubReg(Offset, TRI->getSubRegIdxSize(SubReg));  in shiftSubReg()
283     for (auto [SubReg, SRI] : SubRegs)  in getRegClassWithShiftedSubregs()
285       assert(MinRC == TRI->getSubClassWithSubReg(MinRC, SRI.SubReg));  in getRegClassWithShiftedSubregs()
299   for (auto [SubReg, SRI] : SubRegs) {  in getMinSizeReg()
300     unsigned SubRegOffset = TRI->getSubRegIdxOffset(SubReg);  in getMinSizeReg()
301     unsigned SubRegEnd = SubRegOffset + TRI->getSubRegIdxSize(SubReg);  in getMinSizeReg()
311       CoverSubreg = SubReg;  in getMinSizeReg()
323   for (auto [SubReg, SRI] : SubRegs)  in getMinSizeReg()
324     MaxAlign = std::max(MaxAlign, TRI->getSubRegAlignmentNumBits(RC, SubReg));  in getMinSizeReg()
327   for (auto [SubReg, SRI] : SubRegs) {  in getMinSizeReg()
328     if (TRI->getSubRegAlignmentNumBits(RC, SubReg) != MaxAlign)  in getMinSizeReg()
331         std::min(FirstMaxAlignedSubRegOffset, TRI->getSubRegIdxOffset(SubReg));  in getMinSizeReg()
390     if (unsigned NewSubReg = I->second.SubReg)  in updateLiveIntervals()
426     const unsigned SubReg = MO.getSubReg();  in rewriteReg()  local
427     assert(SubReg != AMDGPU::NoSubRegister); // Due to [1].  in rewriteReg()
428     LLVM_DEBUG(dbgs() << "  " << TRI->getSubRegIndexName(SubReg) << ':');  in rewriteReg()
430     const auto [I, Inserted] = SubRegs.try_emplace(SubReg);  in rewriteReg()
434       SubRegRC = TRI->getSubRegisterClass(RC, SubReg);  in rewriteReg()
469     unsigned SubReg = SubRegs[MO.getSubReg()].SubReg;  in rewriteReg()  local
470     MO.setSubReg(SubReg);  in rewriteReg()
471     if (SubReg == AMDGPU::NoSubRegister && MO.isDef())  in rewriteReg()