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/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp105 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
108 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, in executeFAddInst() argument
119 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, in executeFSubInst() argument
130 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, in executeFMulInst() argument
141 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, in executeFDivInst() argument
152 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, in executeFRemInst() argument
156 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
159 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
169 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
175 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1116 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1150 const SrcOp &Src1, unsigned Index);
1674 const SrcOp &Src1,
1676 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1691 const SrcOp &Src1,
1693 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1707 const SrcOp &Src1,
1709 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1713 const SrcOp &Src1,
1715 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
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H A DGISelKnownBits.h38 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
42 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
H A DMIPatternMatch.h729 Src1Ty Src1;
732 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2)
733 : Src0(Src0), Src1(Src1), Src2(Src2) {}
740 Src1.match(MRI, TmpMI->getOperand(2).getReg()) &&
750 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
752 TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2);
757 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
759 Src0, Src1, Src2);
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp149 Register Src1 = in runOnMachineFunction() local
153 (void) Src1; in runOnMachineFunction()
155 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
156 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
200 unsigned Src1 = 0; in runOnMachineFunction() local
206 Src1 = MI.getOperand(Src1Idx).getReg(); in runOnMachineFunction()
212 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
217 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
252 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
H A DSIOptimizeExecMasking.cpp143 const MachineOperand &Src1 = MI.getOperand(1); in isLogicalOpOnExec() local
144 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
159 const MachineOperand &Src1 = MI.getOperand(1); in isLogicalOpOnExec() local
160 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
537 MachineOperand &Src1 = SaveExecInst->getOperand(2); in optimizeExecSequence() local
542 OtherOp = &Src1; in optimizeExecSequence()
543 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) { in optimizeExecSequence()
584 MachineOperand *Src1 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src1); in optimizeVCMPSaveExecSequence() local
612 Builder.add(*Src1); in optimizeVCMPSaveExecSequence()
619 if (Src1->isReg()) in optimizeVCMPSaveExecSequence()
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H A DAMDGPUInstCombineIntrinsic.cpp45 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN() argument
47 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2); in fmed3AMDGCN()
52 return maxnum(Src1, Src2); in fmed3AMDGCN()
54 APFloat::cmpResult Cmp1 = Max3.compare(Src1); in fmed3AMDGCN()
59 return maxnum(Src0, Src1); in fmed3AMDGCN()
602 Value *Src1 = II.getArgOperand(1); in instCombineIntrinsic() local
603 const ConstantInt *CMask = dyn_cast<ConstantInt>(Src1); in instCombineIntrinsic()
609 II.setArgOperand(1, ConstantInt::get(Src1->getType(), in instCombineIntrinsic()
615 if (isa<PoisonValue>(Src0) || isa<PoisonValue>(Src1)) in instCombineIntrinsic()
619 if (IC.getSimplifyQuery().isUndefValue(Src1)) in instCombineIntrinsic()
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H A DSIShrinkInstructions.cpp247 MachineOperand &Src1 = MI.getOperand(1); in shrinkScalarCompare() local
248 if (!Src1.isImm()) in shrinkScalarCompare()
259 if (isKImmOrKUImmOperand(Src1, HasUImm)) { in shrinkScalarCompare()
263 Src1.setImm(SignExtend32(Src1.getImm(), 32)); in shrinkScalarCompare()
274 if ((SIInstrInfo::sopkIsZext(SOPKOpc) && isKUImmOperand(Src1)) || in shrinkScalarCompare()
275 (!SIInstrInfo::sopkIsZext(SOPKOpc) && isKImmOperand(Src1))) { in shrinkScalarCompare()
277 Src1.setImm(SignExtend64(Src1.getImm(), 32)); in shrinkScalarCompare()
419 MachineOperand &Src1 = *TII->getNamedOperand(MI, AMDGPU::OpName::src1); in shrinkMadFma() local
427 if (Src1.isReg() && TRI->isVGPR(*MRI, Src1.getReg())) in shrinkMadFma()
456 if (Src1.isImm() && !TII->isInlineConstant(Src1)) in shrinkMadFma()
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H A DGCNDPPCombine.cpp314 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst() local
315 if (Src1) { in createDPPInst()
326 if (!TII->isOperandLegal(*DPPInst.getInstr(), OpNum, Src1)) { in createDPPInst()
331 DPPInst.add(*Src1); in createDPPInst()
490 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst() local
491 if (!Src1 || !Src1->isReg()) { in createDPPInst()
499 CombOldVGPR = getRegSubRegPair(*Src1); in createDPPInst()
685 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in combineDPPMov() local
686 if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1] in combineDPPMov()
693 if ((Use == Src0 && ((Src1 && Src1->isIdenticalTo(*Src0)) || in combineDPPMov()
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H A DSIPeepholeSDWA.cpp590 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
592 if (!Src1->isReg() || Src1->getReg().isPhysical() || in matchSDWAOperand()
599 Dst, Src1, *Imm == 16 ? WORD_1 : BYTE_3, UNUSED_PAD); in matchSDWAOperand()
602 Src1, Dst, *Imm == 16 ? WORD_1 : BYTE_3, false, false, in matchSDWAOperand()
627 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
630 if (!Src1->isReg() || Src1->getReg().isPhysical() || in matchSDWAOperand()
636 return std::make_unique<SDWADstOperand>(Dst, Src1, BYTE_1, UNUSED_PAD); in matchSDWAOperand()
638 Src1, Dst, BYTE_1, false, false, in matchSDWAOperand()
660 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in matchSDWAOperand() local
661 auto Offset = foldToImm(*Src1); in matchSDWAOperand()
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H A DAMDGPURegBankCombiner.cpp317 MachineInstr *Src1 = getDefIgnoringCopies(MI.getOperand(2).getReg(), MRI); in matchFPMed3ToClamp() local
320 if (isFCst(Src0) && !isFCst(Src1)) in matchFPMed3ToClamp()
321 std::swap(Src0, Src1); in matchFPMed3ToClamp()
322 if (isFCst(Src1) && !isFCst(Src2)) in matchFPMed3ToClamp()
323 std::swap(Src1, Src2); in matchFPMed3ToClamp()
324 if (isFCst(Src0) && !isFCst(Src1)) in matchFPMed3ToClamp()
325 std::swap(Src0, Src1); in matchFPMed3ToClamp()
326 if (!isClampZeroToOne(Src1, Src2)) in matchFPMed3ToClamp()
H A DAMDGPUCombinerHelper.h31 Register Src1, Register Src2);
33 Register Src1, Register Src2);
H A DAMDGPUCombinerHelper.cpp420 Register Src1, in matchExpandPromotedF16FMed3() argument
427 return isFPExtFromF16OrConst(MRI, Src0) && isFPExtFromF16OrConst(MRI, Src1) && in matchExpandPromotedF16FMed3()
433 Register Src1, in applyExpandPromotedF16FMed3() argument
438 Src1 = Builder.buildFPTrunc(LLT::scalar(16), Src1).getReg(0); in applyExpandPromotedF16FMed3()
442 auto A1 = Builder.buildFMinNumIEEE(Ty, Src0, Src1); in applyExpandPromotedF16FMed3()
443 auto B1 = Builder.buildFMaxNumIEEE(Ty, Src0, Src1); in applyExpandPromotedF16FMed3()
H A DSIFoldOperands.cpp1231 MachineOperand *Src1 = getImmOrMaterializedImm(MI->getOperand(Src1Idx)); in tryConstantFoldOp() local
1233 if (!Src0->isImm() && !Src1->isImm()) in tryConstantFoldOp()
1239 if (Src0->isImm() && Src1->isImm()) { in tryConstantFoldOp()
1241 if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm())) in tryConstantFoldOp()
1257 if (Src0->isImm() && !Src1->isImm()) { in tryConstantFoldOp()
1258 std::swap(Src0, Src1); in tryConstantFoldOp()
1262 int32_t Src1Val = static_cast<int32_t>(Src1->getImm()); in tryConstantFoldOp()
1317 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in tryFoldCndMask() local
1318 if (!Src1->isIdenticalTo(*Src0)) { in tryFoldCndMask()
1320 auto *Src1Imm = getImmOrMaterializedImm(*Src1); in tryFoldCndMask()
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H A DSIInstrInfo.cpp2721 MachineOperand &Src1, in swapSourceModifiers() argument
2788 MachineOperand &Src1 = MI.getOperand(Src1Idx); in commuteInstructionImpl() local
2791 if (Src0.isReg() && Src1.isReg()) { in commuteInstructionImpl()
2798 } else if (Src0.isReg() && !Src1.isReg()) { in commuteInstructionImpl()
2801 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1); in commuteInstructionImpl()
2802 } else if (!Src0.isReg() && Src1.isReg()) { in commuteInstructionImpl()
2804 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0); in commuteInstructionImpl()
2812 Src1, AMDGPU::OpName::src1_modifiers); in commuteInstructionImpl()
3523 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1); in foldImmediate() local
3528 (Src1->isReg() && Src1->getReg() == Reg)) { in foldImmediate()
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H A DSIFixSGPRCopies.cpp709 MachineOperand &Src1 = MI.getOperand(Src1Idx); in runOnMachineFunction() local
714 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) && in runOnMachineFunction()
715 Src1.getReg() != AMDGPU::M0)) { in runOnMachineFunction()
722 for (MachineOperand *MO : {&Src0, &Src1}) { in runOnMachineFunction()
747 .add(Src1); in runOnMachineFunction()
748 Src1.ChangeToRegister(AMDGPU::M0, false); in runOnMachineFunction()
H A DSIISelLowering.cpp4976 MachineOperand &Src1 = MI.getOperand(3); in EmitInstrWithCustomInserter() local
4981 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1); in EmitInstrWithCustomInserter()
4999 MachineOperand &Src1 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
5005 .add(Src1); in EmitInstrWithCustomInserter()
5019 MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
5021 MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
5051 MachineOperand &Src1 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
5058 .add(Src1); in EmitInstrWithCustomInserter()
5075 const TargetRegisterClass *Src1RC = Src1.isReg() in EmitInstrWithCustomInserter()
5076 ? MRI.getRegClass(Src1.getReg()) in EmitInstrWithCustomInserter()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp134 unsigned getMuxOpcode(const MachineOperand &Src1,
205 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1, in getMuxOpcode() argument
207 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
299 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
300 Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); in genMuxInBlock()
317 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
318 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
H A DHexagonPeephole.cpp151 MachineOperand &Src1 = MI.getOperand(1); in runOnMachineFunction() local
153 if (Src1.getImm() != 0) in runOnMachineFunction()
168 MachineOperand &Src1 = MI.getOperand(1); in runOnMachineFunction() local
173 Register SrcReg = Src1.getReg(); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp299 unsigned Src1 = 0, SubReg1; in transformInstruction() local
328 Src1 = MOSrc1->getReg(); in transformInstruction()
347 if (!Src1) { in transformInstruction()
349 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1); in transformInstruction()
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp54 Register Src1) { in PairedCopy() argument
57 if (Dest0 == Src1 && Dest1 == Src0) { in PairedCopy()
62 } else if (Dest0 != Src0 || Dest1 != Src1) { in PairedCopy()
63 if (Dest0 == Src1 || Dest1 != Src0) { in PairedCopy()
64 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
68 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp173 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForMemcmp() argument
181 CCReg = emitMemMemImm(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Bytes); in EmitTargetCodeForMemcmp()
183 CCReg = emitMemMemReg(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Size); in EmitTargetCodeForMemcmp()
225 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForStrcmp() argument
228 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::i32, MVT::Other); in EmitTargetCodeForStrcmp()
230 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1, in EmitTargetCodeForStrcmp()
H A DSystemZSelectionDAGInfo.h39 SDValue Src1, SDValue Src2, SDValue Size,
55 SDValue Src1, SDValue Src2,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp112 void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1, in computeKnownBitsMin() argument
117 computeKnownBitsImpl(Src1, Known, DemandedElts, Depth); in computeKnownBitsMin()
619 unsigned GISelKnownBits::computeNumSignBitsMin(Register Src0, Register Src1, in computeNumSignBitsMin() argument
623 unsigned Src1SignBits = computeNumSignBits(Src1, DemandedElts, Depth); in computeNumSignBitsMin()
747 Register Src1 = MI.getOperand(1).getReg(); in computeNumSignBits() local
749 computeNumSignBits(Src1, DemandedElts, Depth + 1); in computeNumSignBits()
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDevicePathUtilities.h68 IN CONST EFI_DEVICE_PATH_PROTOCOL *Src1,

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