Lines Matching refs:Src1
4976 MachineOperand &Src1 = MI.getOperand(3); in EmitInstrWithCustomInserter() local
4981 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1); in EmitInstrWithCustomInserter()
4999 MachineOperand &Src1 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
5005 .add(Src1); in EmitInstrWithCustomInserter()
5019 MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
5021 MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
5051 MachineOperand &Src1 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
5058 .add(Src1); in EmitInstrWithCustomInserter()
5075 const TargetRegisterClass *Src1RC = Src1.isReg() in EmitInstrWithCustomInserter()
5076 ? MRI.getRegClass(Src1.getReg()) in EmitInstrWithCustomInserter()
5087 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter()
5092 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()
5133 MachineOperand &Src1 = MI.getOperand(3); in EmitInstrWithCustomInserter() local
5144 if (Src1.isReg() && TRI->isVectorRegister(MRI, Src1.getReg())) { in EmitInstrWithCustomInserter()
5147 .addReg(Src1.getReg()); in EmitInstrWithCustomInserter()
5148 Src1.setReg(RegOp1); in EmitInstrWithCustomInserter()
5189 BuildMI(*BB, MII, DL, TII->get(Opc), Dest.getReg()).add(Src0).add(Src1); in EmitInstrWithCustomInserter()
5290 const MachineOperand &Src1 = MI.getOperand(2); in EmitInstrWithCustomInserter() local
5302 const TargetRegisterClass *Src1RC = Src1.isReg() in EmitInstrWithCustomInserter()
5303 ? MRI.getRegClass(Src1.getReg()) in EmitInstrWithCustomInserter()
5314 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter()
5319 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()
6056 SDValue Src1 = N->getOperand(2); in lowerFCMPIntrinsic() local
6062 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1); in lowerFCMPIntrinsic()
6070 Src1, DAG.getCondCode(CCOpcode)); in lowerFCMPIntrinsic()
6123 auto createLaneOp = [&DAG, &SL, N, IID](SDValue Src0, SDValue Src1, in lowerLaneOp()
6137 Operands.push_back(Src1); in lowerLaneOp()
6161 SDValue Src1, Src2; in lowerLaneOp() local
6164 Src1 = N->getOperand(2); in lowerLaneOp()
6180 Src1 = DAG.getAnyExtOrTrunc(IsFloat ? DAG.getBitcast(IntVT, Src1) : Src1, in lowerLaneOp()
6189 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, MVT::i32); in lowerLaneOp()
6242 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VT.getSimpleVT()); in lowerLaneOp()
6256 Src1SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src1, in lowerLaneOp()
6266 : createLaneOp(Src0SubVec, Src1, Src2SubVec, SubVecVT)); in lowerLaneOp()
6281 Src1 = DAG.getBitcast(VecVT, Src1); in lowerLaneOp()
6286 SDValue LaneOp = createLaneOp(Src0, Src1, Src2, VecVT); in lowerLaneOp()
6313 SDValue Src1 = N->getOperand(2); in ReplaceNodeResults() local
6316 Src0, Src1); in ReplaceNodeResults()
6325 SDValue Src1 = N->getOperand(2); in ReplaceNodeResults() local
6340 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1)); in ReplaceNodeResults()
6342 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1); in ReplaceNodeResults()
9498 SDValue Src1 = Op.getOperand(5); in LowerINTRINSIC_VOID() local
9508 DAG.getNode(ISD::BITCAST, DL, MVT::f32, Src1), // src1 in LowerINTRINSIC_VOID()
10574 SDValue Src1 = Op.getOperand(1); in LowerFDIV16() local
10577 SDValue CvtSrc1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1); in LowerFDIV16()
10585 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0); in LowerFDIV16()
13276 SDValue Src1 = N->getOperand(1); in performFMed3Combine() local
13279 if (isClampZeroToOne(Src0, Src1)) { in performFMed3Combine()
13294 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1)) in performFMed3Combine()
13295 std::swap(Src0, Src1); in performFMed3Combine()
13297 if (isa<ConstantFPSDNode>(Src1) && !isa<ConstantFPSDNode>(Src2)) in performFMed3Combine()
13298 std::swap(Src1, Src2); in performFMed3Combine()
13300 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1)) in performFMed3Combine()
13301 std::swap(Src0, Src1); in performFMed3Combine()
13303 if (isClampZeroToOne(Src1, Src2)) in performFMed3Combine()
13313 SDValue Src1 = N->getOperand(1); in performCvtPkRTZCombine() local
13314 if (Src0.isUndef() && Src1.isUndef()) in performCvtPkRTZCombine()
13817 ByteProvider<SDValue> &Src1, in placeSources() argument
13821 assert(Src0.Src.has_value() && Src1.Src.has_value()); in placeSources()
13826 Src1s.push_back({*Src1.Src, ((Src1.SrcOffset % 4) << 24) + 0x0c0c0c, in placeSources()
13827 Src1.SrcOffset / 4}); in placeSources()
13832 std::pair<ByteProvider<SDValue>, ByteProvider<SDValue>> BPP = {Src0, Src1}; in placeSources()
13834 BPP = {Src1, Src0}; in placeSources()
13885 Src1.SrcOffset / 4}); in placeSources()
13887 {*Src1.Src, in placeSources()
13888 ((Src1.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask)), in placeSources()
13889 Src1.SrcOffset / 4}); in placeSources()
13979 ByteProvider<SDValue> &Src1, const SDValue &S0Op, in checkDot4MulSignedness() argument
14076 auto Src1 = handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(1)); in performAddCombine() local
14077 if (!Src1) in performAddCombine()
14081 TempNode->getOperand(MulIdx), *Src0, *Src1, in performAddCombine()
14090 placeSources(*Src0, *Src1, Src0s, Src1s, I); in performAddCombine()
14100 auto Src1 = in performAddCombine() local
14102 if (!Src1) in performAddCombine()
14105 TempNode->getOperand(AddIdx), *Src0, *Src1, in performAddCombine()
14113 placeSources(*Src0, *Src1, Src0s, Src1s, I + 1); in performAddCombine()
14139 SDValue Src0, Src1; in performAddCombine() local
14176 Src1 = DAG.getBitcastedAnyExtOrTrunc(SecondEltOp, SL, in performAddCombine()
14183 Src1 = resolveSources(DAG, SL, Src1s, false, true); in performAddCombine()
14196 Src1, Src2, DAG.getTargetConstant(0, SL, MVT::i1)); in performAddCombine()
15065 SDValue Src1 = Node->getOperand(3); in PostISelFolding() local
15070 (Src0 == Src1 || Src0 == Src2)) in PostISelFolding()
15087 if (Src1.isMachineOpcode() && in PostISelFolding()
15088 Src1.getMachineOpcode() != AMDGPU::IMPLICIT_DEF) in PostISelFolding()
15089 Src0 = Src1; in PostISelFolding()
15094 assert(Src1.getMachineOpcode() == AMDGPU::IMPLICIT_DEF); in PostISelFolding()
15096 Src1 = UndefReg; in PostISelFolding()
15103 Ops[3] = Src1; in PostISelFolding()
15829 auto [Dst, Src0, Src1, Src2] = MI->getFirst4Regs(); in computeKnownBitsForTargetInstr()
15837 KB.computeKnownBitsImpl(Src1, Known1, DemandedElts, Depth + 1); in computeKnownBitsForTargetInstr()