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Searched refs:SchedRead (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td121 def ReadSFBJmp : SchedRead;
122 def ReadSFBALU : SchedRead;
125 def ReadJmp : SchedRead;
126 def ReadJalr : SchedRead;
127 def ReadCSR : SchedRead;
128 def ReadMemBase : SchedRead;
129 def ReadFMemBase : SchedRead;
130 def ReadStoreData : SchedRead;
131 def ReadFStoreData : SchedRead;
132 def ReadIALU : SchedRead;
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H A DRISCVScheduleZb.td51 def ReadSHXADD : SchedRead; // sh1add/sh2add/sh3add
52 def ReadSHXADD32 : SchedRead; // sh1add.uw/sh2add.uw/sh3add.uw
55 def ReadRotateImm : SchedRead;
56 def ReadRotateImm32 : SchedRead;
57 def ReadRotateReg : SchedRead;
58 def ReadRotateReg32 : SchedRead;
59 def ReadCLZ : SchedRead;
60 def ReadCLZ32 : SchedRead;
61 def ReadCTZ : SchedRead;
62 def ReadCTZ32 : SchedRead;
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H A DRISCVScheduleV.td116 // Define multiclasses to define SchedWrite, SchedRead, WriteRes, and
127 def name # "_WorstCase" : SchedRead;
129 def name # "_" # mx : SchedRead;
142 if !exists<SchedRead>(name # "_WorstCase") then
143 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
145 if !exists<SchedRead>(name # "_" # mx) then
146 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>;
150 // Define multiclasses to define SchedWrite, SchedRead, WriteRes, and
164 def name # "_WorstCase" : SchedRead;
167 def name # "_" # mx # "_E" # sew : SchedRead;
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H A DRISCVInstrInfoV.td103 class SchedCommon<list<SchedWrite> writes, list<SchedRead> reads,
109 !cast<SchedRead>("ReadVMergeOp_" # mx),
110 !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" #sew));
128 !cast<SchedRead>(!if(sew, read #"_" #mx #"_E" #sew,
170 !listsplat(!cast<SchedRead>(read), 3), mx, sew, forceMergeOpRead>;
173 [!cast<SchedRead>(readV), !cast<SchedRead>(readV0)],
179 [!cast<SchedRead>("ReadVMov" # n # "V")]
191 [!cast<SchedRead>("ReadVSTEV_" # lmul), ReadVSTX], mx=lmul,
205 [!cast<SchedRead>("ReadVSTS" # eew # "V_" # emul), ReadVSTX, ReadVSTSX],
214 [ReadVLDX, !cast<SchedRead>("ReadVLD" # !if(isOrdered, "O", "U") # "XV_" # idxEMUL)],
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H A DRISCVSchedXiangShanNanHu.td211 class XS2LoadToALUBypass<SchedRead read>
H A DRISCVSchedSiFive7.td178 class SiFive7AnyToGPRBypass<SchedRead read, int cycles = 2>
1292 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>;
1294 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>;
H A DRISCVSchedSiFiveP600.td1091 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>;
1093 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td27 def ReadI : SchedRead; // ALU
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
29 def ReadIEReg : SchedRead; // ALU of Extended-Reg
31 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
35 def ReadID : SchedRead; // 32/64-bit Divide
38 def ReadIM : SchedRead; // 32/64-bit Multiply
39 def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate
50 def ReadST : SchedRead; // Read the stored value.
51 def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
88 def ReadVLD : SchedRead;
H A DAArch64SchedThunderX.td191 // Subtarget-specific SchedRead types.
H A DAArch64SchedA53.td149 // Subtarget-specific SchedRead types.
H A DAArch64SchedA55.td208 // Subtarget-specific SchedRead types.
H A DAArch64SchedCyclone.td865 // Unused SchedRead types
H A DAArch64SchedA510.td221 // Subtarget-specific SchedRead types.
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td13 def P10BR_Read : SchedRead;
14 def P10DF_Read : SchedRead;
15 def P10DV_Read : SchedRead;
16 def P10DX_Read : SchedRead;
17 def P10F2_Read : SchedRead;
18 def P10FX_Read : SchedRead;
19 def P10LD_Read : SchedRead;
20 def P10MU_Read : SchedRead;
21 def P10PM_Read : SchedRead;
22 def P10ST_Read : SchedRead;
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSchedule.td213 // listed for implicit def operands. SchedRead types may optionally
219 // single SchedWrite and single SchedRead in any order.
229 class SchedRead : SchedReadWrite;
333 // A processor may define a ReadAdvance associated with a SchedRead
343 class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
345 SchedRead ReadType = read;
348 // Directly associate a new SchedRead type with a delay and optional
350 class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead,
353 // Define SchedRead defaults. Reads seldom need special treatment.
354 def ReadDefault : SchedRead;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSchedule.td61 def ReadALU : SchedRead;
67 def ReadALUsr : SchedRead; // Some operands are read later.
79 def ReadMUL : SchedRead;
86 def ReadMAC : SchedRead;
118 def ReadFPMUL : SchedRead; // multiplier read
119 def ReadFPMAC : SchedRead; // accumulator read
H A DARMScheduleR52.td9 // This file defines the SchedRead/Write data for the ARM Cortex-R52 processor.
46 def R52Read_ISS : SchedRead;
47 def R52Read_EX1 : SchedRead;
48 def R52Read_EX2 : SchedRead;
49 def R52Read_WRI : SchedRead;
50 def R52Read_F0 : SchedRead; // F0 maps to ISS stage of integer pipe
51 def R52Read_F1 : SchedRead;
52 def R52Read_F2 : SchedRead;
H A DARMScheduleM4.td9 // This file defines the SchedRead/Write data for the ARM Cortex-M4 processor.
H A DARMScheduleM7.td9 // This file defines the SchedRead/Write data for the ARM Cortex-M7 processor.
H A DARMScheduleA57.td774 // def A57ReadVFMA : SchedRead;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Schedule.td15 def ReadAfterLd : SchedRead;
16 def ReadAfterVecLd : SchedRead;
17 def ReadAfterVecXLd : SchedRead;
18 def ReadAfterVecYLd : SchedRead;
22 // This SchedRead describes a bypass delay caused by data being moved from the
24 def ReadInt2Fpu : SchedRead;
48 // The SchedRead to tag register operands than don't need to be ready
50 SchedRead ReadAfterFold;
54 multiclass X86SchedWritePair<SchedRead ReadAfter = ReadAfterLd> {
H A DX86InstrSSE.td859 SchedRead Int2Fpu = ReadDefault> {
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp119 Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
943 Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, in FindReadAdvance() argument
946 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) in FindReadAdvance()
947 return SchedRead.TheDef; in FindReadAdvance()
951 for (Record *A : SchedRead.Aliases) { in FindReadAdvance()
976 if (AliasDef == RADef || SchedRead.TheDef == RADef) { in FindReadAdvance()
992 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") { in FindReadAdvance()
995 SchedRead.TheDef->getName()); in FindReadAdvance()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSchedule.td35 def RegReadAdv : SchedRead;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSISchedule.td27 def MIVGPRRead : SchedRead;
28 def MIMFMARead : SchedRead;