10b57cec5SDimitry Andric//==-- SystemZSchedule.td - SystemZ Scheduling Definitions ----*- tblgen -*-==// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 90b57cec5SDimitry Andric// Scheduler resources 100b57cec5SDimitry Andric 110b57cec5SDimitry Andric// These resources are used to express decoder grouping rules. The number of 120b57cec5SDimitry Andric// decoder slots needed by an instructions is normally one, but there are 130b57cec5SDimitry Andric// exceptions. 140b57cec5SDimitry Andricdef NormalGr : SchedWrite; 150b57cec5SDimitry Andricdef Cracked : SchedWrite; 160b57cec5SDimitry Andricdef GroupAlone : SchedWrite; 170b57cec5SDimitry Andricdef GroupAlone2 : SchedWrite; 180b57cec5SDimitry Andricdef GroupAlone3 : SchedWrite; 190b57cec5SDimitry Andricdef BeginGroup : SchedWrite; 200b57cec5SDimitry Andricdef EndGroup : SchedWrite; 210b57cec5SDimitry Andric 220b57cec5SDimitry Andric// A SchedWrite added to other SchedWrites to make LSU latency parameterizable. 230b57cec5SDimitry Andricdef LSULatency : SchedWrite; 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric// Operand WriteLatencies. 260b57cec5SDimitry Andricforeach L = 1 - 30 in def "WLat"#L : SchedWrite; 270b57cec5SDimitry Andric 280b57cec5SDimitry Andricforeach L = 1 - 16 in 290b57cec5SDimitry Andric def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L), 300b57cec5SDimitry Andric LSULatency]>; 310b57cec5SDimitry Andric 320b57cec5SDimitry Andric// ReadAdvances, used for the register operand next to a memory operand, 330b57cec5SDimitry Andric// modelling that the register operand is needed later than the address 340b57cec5SDimitry Andric// operands. 350b57cec5SDimitry Andricdef RegReadAdv : SchedRead; 360b57cec5SDimitry Andric 370b57cec5SDimitry Andricforeach Num = ["", "2", "3", "4", "5", "6"] in { 380b57cec5SDimitry Andric // Fixed-point units 390b57cec5SDimitry Andric def "FXa"#Num : SchedWrite; 400b57cec5SDimitry Andric def "FXb"#Num : SchedWrite; 410b57cec5SDimitry Andric def "FXU"#Num : SchedWrite; 420b57cec5SDimitry Andric // Load/store unit 430b57cec5SDimitry Andric def "LSU"#Num : SchedWrite; 440b57cec5SDimitry Andric // Vector sub units (z13 and later) 450b57cec5SDimitry Andric def "VecBF"#Num : SchedWrite; 460b57cec5SDimitry Andric def "VecDF"#Num : SchedWrite; 470b57cec5SDimitry Andric def "VecDFX"#Num : SchedWrite; 480b57cec5SDimitry Andric def "VecMul"#Num : SchedWrite; 490b57cec5SDimitry Andric def "VecStr"#Num : SchedWrite; 500b57cec5SDimitry Andric def "VecXsPm"#Num : SchedWrite; 510b57cec5SDimitry Andric // Floating point unit (zEC12 and earlier) 520b57cec5SDimitry Andric def "FPU"#Num : SchedWrite; 530b57cec5SDimitry Andric def "DFU"#Num : SchedWrite; 540b57cec5SDimitry Andric} 550b57cec5SDimitry Andric 56*81ad6265SDimitry Andricdef VecFPd : SchedWrite; // Blocking BFP div/sqrt unit (30 cycles). 57*81ad6265SDimitry Andricdef VecFPd20 : SchedWrite; // Blocking BFP div/sqrt unit, 20 cycles. 580b57cec5SDimitry Andric 590b57cec5SDimitry Andricdef VBU : SchedWrite; // Virtual branching unit 600b57cec5SDimitry Andric 610b57cec5SDimitry Andricdef MCD : SchedWrite; // Millicode 620b57cec5SDimitry Andric 63*81ad6265SDimitry Andricinclude "SystemZScheduleZ16.td" 648bcb0991SDimitry Andricinclude "SystemZScheduleZ15.td" 650b57cec5SDimitry Andricinclude "SystemZScheduleZ14.td" 660b57cec5SDimitry Andricinclude "SystemZScheduleZ13.td" 670b57cec5SDimitry Andricinclude "SystemZScheduleZEC12.td" 680b57cec5SDimitry Andricinclude "SystemZScheduleZ196.td" 69