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Searched refs:SVT (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSymbolXCOFF.h57 void setVisibilityType(XCOFF::VisibilityType SVT) { VisibilityType = SVT; }; in setVisibilityType() argument
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp927 MVT SVT = VT.getSimpleVT(); in getTypeConversion() local
928 assert((unsigned)SVT.SimpleTy < std::size(TransformToType)); in getTypeConversion()
929 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
930 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); in getTypeConversion()
939 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context)); in getTypeConversion()
941 return LegalizeKind(LA, SVT.getVectorElementType()); in getTypeConversion()
1397 MVT SVT = (MVT::SimpleValueType) nVT; in computeRegisterProperties() local
1400 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() && in computeRegisterProperties()
1401 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) { in computeRegisterProperties()
1402 TransformToType[i] = SVT; in computeRegisterProperties()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp937 EVT SVT = N->getOperand(IsStrict ? 1 : 0).getValueType(); in SoftenFloatRes_XINT_TO_FP() local
950 if (NVT.bitsGE(SVT)) in SoftenFloatRes_XINT_TO_FP()
961 CallOptions.setTypeListBeforeSoften(SVT, RVT, true); in SoftenFloatRes_XINT_TO_FP()
1064 EVT SVT = Op.getValueType(); in SoftenFloatOp_FP_ROUND() local
1074 RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, FloatRVT); in SoftenFloatOp_FP_ROUND()
1080 CallOptions.setTypeListBeforeSoften(SVT, RVT, true); in SoftenFloatOp_FP_ROUND()
1140 EVT SVT = Op.getValueType(); in SoftenFloatOp_FP_TO_XINT() local
1149 RTLIB::Libcall LC = findFPToIntLibcall(SVT, RVT, NVT, Signed); in SoftenFloatOp_FP_TO_XINT()
1156 CallOptions.setTypeListBeforeSoften(SVT, RVT, true); in SoftenFloatOp_FP_TO_XINT()
3243 EVT SVT = N->getOperand(0).getValueType(); in SoftPromoteHalfRes_FP_ROUND() local
[all …]
H A DSelectionDAG.cpp368 EVT SVT = Op.getValueType().getScalarType(); in matchUnaryPredicateImpl() local
377 if (!Cst || Cst->getValueType(0) != SVT || !Match(Cst)) in matchUnaryPredicateImpl()
406 EVT SVT = LHS.getValueType().getScalarType(); in matchBinaryPredicate() local
416 if (!AllowTypeMismatch && (LHSOp.getValueType() != SVT || in matchBinaryPredicate()
2998 EVT SVT = SrcVector.getValueType().getScalarType(); in getSplatValue() local
2999 EVT LegalSVT = SVT; in getSplatValue()
3000 if (LegalTypes && !TLI->isTypeLegal(SVT)) { in getSplatValue()
3001 if (!SVT.isInteger()) in getSplatValue()
3004 if (LegalSVT.bitsLT(SVT)) in getSplatValue()
5847 EVT SVT = VT.getScalarType(); in foldCONCAT_VECTORS() local
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H A DLegalizeDAG.cpp331 EVT SVT = VT; in ExpandConstantFP() local
336 while (SVT != MVT::f32 && SVT != MVT::f16 && SVT != MVT::bf16) { in ExpandConstantFP()
337 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
338 if (ConstantFPSDNode::isValueValidForType(SVT, APF) && in ExpandConstantFP()
341 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
343 Type *SType = SVT.getTypeForEVT(*DAG.getContext()); in ExpandConstantFP()
346 VT = SVT; in ExpandConstantFP()
895 EVT SVT = SrcVT.getScalarType(); in LegalizeLoadOps() local
896 if (SVT == MVT::f16 || SVT == MVT::bf16) { in LegalizeLoadOps()
904 DAG.getNode(SVT == MVT::f16 ? ISD::FP16_TO_FP : ISD::BF16_TO_FP, in LegalizeLoadOps()
[all …]
H A DLegalizeIntegerTypes.cpp415 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType()); in PromoteIntRes_AtomicCmpSwap() local
420 if (!TLI.isTypeLegal(SVT)) in PromoteIntRes_AtomicCmpSwap()
421 SVT = NVT; in PromoteIntRes_AtomicCmpSwap()
423 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other); in PromoteIntRes_AtomicCmpSwap()
802 EVT SVT = In.getValueType().getScalarType(); in PromoteIntRes_EXTRACT_VECTOR_ELT() local
803 if (SVT.bitsGE(NVT)) { in PromoteIntRes_EXTRACT_VECTOR_ELT()
804 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
1014 EVT SVT = getSetCCResultType(VT); in PromoteIntRes_Overflow() local
1022 SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT), in PromoteIntRes_Overflow()
1339 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC() local
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H A DTargetLowering.cpp6102 EVT SVT = VT.getScalarType(); in BuildExactSDIV() local
6120 Factors.push_back(DAG.getConstant(Factor, dl, SVT)); in BuildExactSDIV()
6162 EVT SVT = VT.getScalarType(); in BuildExactUDIV() local
6181 Factors.push_back(DAG.getConstant(Factor, dl, SVT)); in BuildExactUDIV()
6291 EVT SVT = VT.getScalarType(); in BuildSDIV() local
6344 MagicFactors.push_back(DAG.getConstant(magics.Magic, dl, SVT)); in BuildSDIV()
6345 Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT)); in BuildSDIV()
6347 ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT)); in BuildSDIV()
6453 EVT SVT = VT.getScalarType(); in BuildUDIV() local
6502 MagicFactor = NPQFactor = DAG.getUNDEF(SVT); in BuildUDIV()
[all …]
H A DDAGCombiner.cpp12912 EVT SVT = VT.getScalarType(); in tryToFoldExtendOfConstant() local
12913 if (!(VT.isVector() && (!LegalTypes || TLI.isTypeLegal(SVT)) && in tryToFoldExtendOfConstant()
12918 unsigned VTBits = SVT.getSizeInBits(); in tryToFoldExtendOfConstant()
12927 Elts.push_back(DAG.getUNDEF(SVT)); in tryToFoldExtendOfConstant()
12929 Elts.push_back(DAG.getConstant(0, DL, SVT)); in tryToFoldExtendOfConstant()
12938 Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT)); in tryToFoldExtendOfConstant()
12940 Elts.push_back(DAG.getConstant(C.zext(VTBits), DL, SVT)); in tryToFoldExtendOfConstant()
13461 EVT SVT = getSetCCResultType(N00VT); in foldSextSetcc() local
13464 if (SVT != N0.getValueType()) { in foldSextSetcc()
13470 if (VT.getSizeInBits() == SVT.getSizeInBits()) in foldSextSetcc()
[all …]
H A DLegalizeVectorTypes.cpp7113 EVT SVT = getSetCCResultType(InOp0.getValueType()); in WidenVecOp_SETCC()
7116 SVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, in WidenVecOp_SETCC()
7117 SVT.getVectorElementCount()); in WidenVecOp_SETCC()
7120 SVT, InOp0, InOp1, N->getOperand(2)); in WidenVecOp_SETCC()
7124 SVT.getVectorElementType(), in WidenVecOp_SETCC()
7109 EVT SVT = getSetCCResultType(InOp0.getValueType()); WidenVecOp_SETCC() local
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h41 constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {} in EVT()
H A DSelectionDAG.h1427 MachinePointerInfo PtrInfo, EVT SVT, Align Alignment,
1432 MachinePointerInfo PtrInfo, EVT SVT,
1436 return getTruncStore(Chain, dl, Val, Ptr, PtrInfo, SVT,
1437 Alignment.value_or(getEVTAlign(SVT)), MMOFlags,
1441 SDValue Ptr, EVT SVT, MachineMemOperand *MMO);
1493 MachinePointerInfo PtrInfo, EVT SVT, Align Alignment,
1497 SDValue Ptr, SDValue Mask, SDValue EVL, EVT SVT,
1522 SDValue EVL, EVT SVT, MachineMemOperand *MMO,
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h56 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp205 Type *SVT = VT->getElementType(); in simplifyX86immShift() local
208 unsigned BitWidth = SVT->getPrimitiveSizeInBits(); in simplifyX86immShift()
218 Amt = Builder.CreateZExtOrTrunc(Amt, SVT); in simplifyX86immShift()
227 Amt = ConstantInt::get(SVT, BitWidth - 1); in simplifyX86immShift()
234 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift()
261 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift()
288 auto ShiftAmt = ConstantInt::get(SVT, Count.zextOrTrunc(BitWidth)); in simplifyX86immShift()
353 Type *SVT = VT->getElementType(); in simplifyX86varShift() local
355 int BitWidth = SVT->getIntegerBitWidth(); in simplifyX86varShift()
407 ConstantVec.push_back(UndefValue::get(SVT)); in simplifyX86varShift()
[all …]
H A DX86ISelLowering.cpp4024 MVT SVT = Vec.getSimpleValueType().getScalarType(); in widenSubVector() local
4025 MVT VT = MVT::getVectorVT(SVT, WideNumElts); in widenSubVector()
4265 MVT SVT = VT.getScalarType(); in getAVX512Node() local
4274 !DAG.getTargetLoweringInfo().isTypeLegal(SVT)) in getAVX512Node()
4295 DstVT = MVT::getVectorVT(SVT, 512 / SVT.getSizeInBits()); in getAVX512Node()
12591 MVT SVT = VT.getScalarType(); in lowerShuffleAsBroadcast() local
12592 unsigned Offset = BroadcastIdx * SVT.getStoreSize(); in lowerShuffleAsBroadcast()
12604 X86ISD::VBROADCAST_LOAD, DL, Tys, Ops, SVT, in lowerShuffleAsBroadcast()
12606 Ld->getMemOperand(), Offset, SVT.getStoreSize())); in lowerShuffleAsBroadcast()
12610 assert(SVT == MVT::f64 && "Unexpected VT!"); in lowerShuffleAsBroadcast()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1346 EVT SVT = (UW == 32 || UW == 64) ? MVT::getIntegerVT(UW) : UVT; in ppHoistZextI1() local
1347 SDValue Sel = DAG.getNode(ISD::SELECT, dl, SVT, OpI1, in ppHoistZextI1()
1348 DAG.getBitcast(SVT, If1), in ppHoistZextI1()
1349 DAG.getBitcast(SVT, If0)); in ppHoistZextI1()
H A DHexagonISelLowering.cpp3801 MVT SVT = VT.getSimpleVT(); in allowsMemoryAccess()
3802 if (Subtarget.isHVXVectorType(SVT, true)) in allowsMemoryAccess()
3803 return allowsHvxMemoryAccess(SVT, Flags, Fast); in allowsMemoryAccess()
3813 MVT SVT = VT.getSimpleVT(); in allowsMisalignedMemoryAccesses()
3814 if (Subtarget.isHVXVectorType(SVT, true)) in allowsMisalignedMemoryAccesses()
3815 return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast); in allowsMisalignedMemoryAccesses()
3799 MVT SVT = VT.getSimpleVT(); allowsMemoryAccess() local
3809 MVT SVT = VT.getSimpleVT(); allowsMisalignedMemoryAccesses() local
H A DHexagonISelDAGToDAGHVX.cpp1178 MVT::SimpleValueType SVT = MVT::SimpleValueType(R.OpN & OpRef::Index); in materialize() local
1179 Ops.push_back(ISel.selectUndef(dl, MVT(SVT))); in materialize()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/
H A DGlobalISelMatchTable.cpp429 std::optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) { in MVTToLLT() argument
430 MVT VT(SVT); in MVTToLLT()
H A DGlobalISelMatchTable.h283 std::optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT);
/freebsd/contrib/file/magic/Magdir/
H A Dsysex211 >>>4 byte 0x04 SVT (Velocity Curve)
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5113 MVT SVT = VT.getVectorElementType(); in lowerVECTOR_SHUFFLE()
5131 Offset *= SVT.getStoreSize(); in lowerVECTOR_SHUFFLE()
5136 if (SVT.isInteger() && SVT.bitsGT(XLenVT)) { in lowerVECTOR_SHUFFLE()
5147 ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, SVT, in lowerVECTOR_SHUFFLE()
5149 Ld->getMemOperand(), Offset, SVT.getStoreSize())); in lowerVECTOR_SHUFFLE()
5157 if (SVT == MVT::f16 && !Subtarget.hasStdExtZfh()) { in lowerVECTOR_SHUFFLE()
5158 SVT = MVT::i16; in lowerVECTOR_SHUFFLE()
5159 SplatVT = ContainerVT.changeVectorElementType(SVT); in lowerVECTOR_SHUFFLE()
5165 if (SVT in lowerVECTOR_SHUFFLE()
5112 MVT SVT = VT.getVectorElementType(); lowerVECTOR_SHUFFLE() local
5388 MVT SVT = VT.getSimpleVT(); isShuffleMaskLegal() local
21292 EVT SVT = VT.getScalarType(); isFMAFasterThanFMulAndFAdd() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7084 static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT, in getRegClassForSVT() argument
7088 assert((IsPPC64 || SVT != MVT::i64) && in getRegClassForSVT()
7091 switch (SVT) { in getRegClassForSVT()
7275 MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy; in LowerFormalArguments_AIX() local
7277 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7413 MVT::SimpleValueType SVT = ValVT.SimpleTy; in LowerFormalArguments_AIX() local
7416 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
11915 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), in ReplaceNodeResults() local
11917 SDVTList VTs = DAG.getVTList(SVT, MVT::Other); in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp423 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; in allowsMisalignedMemoryAccesses() local
437 switch (SVT) { in allowsMisalignedMemoryAccesses()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp14929 MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT(); in adjustWritemask() local
14932 SVT : MVT::getVectorVT(SVT, NewChannels == 3 ? 4 : in adjustWritemask()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8802 EVT SVT = VT.getScalarType() == MVT::i8 || VT.getScalarType() == MVT::i16 in LowerVECTOR_SHUFFLEUsingOneOff() local
8806 ISD::EXTRACT_VECTOR_ELT, dl, SVT, in LowerVECTOR_SHUFFLEUsingOneOff()
20678 const SDNode *N, MVT::SimpleValueType SVT) { in getDivRemLibcall() argument
20685 switch (SVT) { in getDivRemLibcall()

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