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Searched refs:SHL (Results 1 – 25 of 113) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h34 SHL = 0x17,
91 case SHL: in lanaiAluCodeToString()
111 .Case("sh", SHL) in stringToLanaiAluCode()
35 SHL = 0x17, global() enumerator
H A DLanaiISelDAGToDAG.cpp235 case ISD::SHL: in isdToLanaiAluCode()
236 return AluCode::SHL; in isdToLanaiAluCode()
H A DLanaiISelLowering.cpp948 Res = DAG.getNode(ISD::SHL, DL, VT, V, in LowerMUL()
961 DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32)); in LowerMUL()
1265 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerSHL_PARTS()
1269 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerSHL_PARTS()
1277 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); in LowerSHL_PARTS()
1316 DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32); in LowerSRL_PARTS()
H A DLanaiMemAluCombiner.cpp219 return LPAC::SHL; in mergedAluCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp375 { ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
378 { ISD::SHL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
381 { ISD::SHL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
393 { ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
396 { ISD::SHL, MVT::v32i8, { 1, 8, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
399 { ISD::SHL, MVT::v64i8, { 1, 8, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
403 { ISD::SHL, MVT::v16i16, { 1, 1, 1, 1 } }, // psllw in getArithmeticInstrCost()
406 { ISD::SHL, MVT::v32i16, { 1, 1, 1, 1 } }, // psllw in getArithmeticInstrCost()
418 { ISD::SHL, MVT::v64i8, { 2, 12, 5, 6 } }, // psllw + pand. in getArithmeticInstrCost()
422 { ISD::SHL, MVT::v16i16, { 2, 7, 4, 4 } }, // psllw + split. in getArithmeticInstrCost()
[all …]
H A DX86ISelDAGToDAG.cpp733 if (U->getOperand(0).getOpcode() == ISD::SHL && in IsProfitableToFold()
737 if (U->getOperand(1).getOpcode() == ISD::SHL && in IsProfitableToFold()
759 case ISD::SHL: in IsProfitableToFold()
1159 case ISD::SHL: in PreprocessISelDAG()
1170 case ISD::SHL: NewOpc = X86ISD::VSHLV; break; in PreprocessISelDAG()
2064 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Ext, ShlCount); in foldMaskAndShiftToExtract()
2108 if (Shift.getOpcode() != ISD::SHL || in foldMaskedShiftToScaledMask()
2135 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); in foldMaskedShiftToScaledMask()
2249 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewExt, NewSHLAmt); in foldMaskAndShiftToScale()
2311 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewExt, NewSHLAmt); in foldMaskedShiftToBEXTR()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp612 if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL) in SelectSHL()
1033 case ISD::SHL: return SelectSHL(N); in Select()
1186 if (T1.getOpcode() != ISD::SHL) in ppAddrReorderAddShl()
1211 SDValue NewShl = DAG.getNode(ISD::SHL, DL, VT, NewAdd, C); in ppAddrReorderAddShl()
1287 SDValue NewShl = DAG.getNode(ISD::SHL, dl, VT, NewSrl, DC); in ppAddrRewriteAndSrl()
1773 case ISD::SHL: in isOpcodeHandled()
1900 if (Val.getOpcode() != ISD::SHL || in findSHL()
1967 if (Val.getOpcode() == ISD::SHL) { in getPowerOf2Factor()
1986 } else if (V.getOpcode() == ISD::SHL) { in willShiftRightEliminate()
2007 } else if (V.getOpcode() == ISD::SHL) { in factorOutPowerOf2()
[all …]
/freebsd/crypto/openssl/crypto/bn/asm/
H A Dppc.pl126 $SHL= "slw"; # shift left
150 $SHL= "sld"; # shift left
1662 $SHL r3,r3,r7 # h = (h<< i)
1664 $SHL r5,r5,r7 # d<<=i
1666 $SHL r4,r4,r7 # l <<=i
H A Dbn-c64xplus.asm195 [!A2] SHL A6,A0,A6 ; normalize dv
199 ||[!A2] SHL A4,1,A5:A4 ; lo<<1
208 || SHL A4,1,A5:A4 ; lo<<1
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrShiftRotate.td15 /// SHL [~] ASR [~] LSR [~] SWAP [ ]
93 defm SHL : MxSROp<"lsl", shl, MxRODI_L, MxROOP_LS>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp86 setOperationAction(ISD::SHL, MVT::i8, Custom); in AVRTargetLowering()
89 setOperationAction(ISD::SHL, MVT::i16, Custom); in AVRTargetLowering()
92 setOperationAction(ISD::SHL, MVT::i32, Custom); in AVRTargetLowering()
292 case ISD::SHL: { in LowerShifts()
307 case ISD::SHL: in LowerShifts()
327 case ISD::SHL: in LowerShifts()
371 case ISD::SHL: in LowerShifts()
380 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { in LowerShifts()
393 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) { in LowerShifts()
465 case ISD::SHL: in LowerShifts()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h26 case ISD::SHL: return ARM_AM::lsl; in getShiftOpcForNode()
H A DARMISelLowering.cpp204 setOperationAction(ISD::SHL, VT, Custom); in addTypeForNEON()
267 setOperationAction(ISD::SHL, VT, Custom); in addMVEVectorTypes()
1009 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT, in ARMTargetLowering()
1188 setOperationAction(ISD::SHL, MVT::i64, Custom); in ARMTargetLowering()
1608 setTargetDAGCombine(ISD::SHL); in ARMTargetLowering()
2022 if (Op.getOpcode() != ISD::SHL) in isSHL16()
3660 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex, in LowerGlobalTLSAddressWindows()
4139 SDValue SHL = in LowerINTRINSIC_WO_CHAIN() local
4140 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy)); in LowerINTRINSIC_WO_CHAIN()
4142 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy)); in LowerINTRINSIC_WO_CHAIN()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp165 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM, in addIPMSequence() local
167 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp108 case ISD::SHL: in PromoteIntegerResult()
696 Op = DAG.getNode(ISD::SHL, dl, NVT, Op, ShiftConst); in PromoteIntRes_CTLZ()
1101 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
1104 matcher.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
1149 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, in PromoteIntRes_MULFIX()
1250 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, in PromoteIntRes_DIVFIX()
1557 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, HiShift); in PromoteIntRes_FunnelShift()
1560 Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amt); in PromoteIntRes_FunnelShift()
1568 Lo = DAG.getNode(ISD::SHL, DL, VT, Lo, ShiftOffset); in PromoteIntRes_FunnelShift()
1881 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, in PromoteIntRes_VAARG()
[all …]
H A DTargetLowering.cpp796 case ISD::SHL: { in SimplifyMultipleUseDemandedBits()
1615 if ((Op0Opcode == ISD::SRL || Op0Opcode == ISD::SHL) && Op0.hasOneUse()) { in SimplifyDemandedBits()
1623 Ones = Op0Opcode == ISD::SHL ? Ones.shl(ShiftAmt) in SimplifyDemandedBits()
1732 case ISD::SHL: { in SimplifyDemandedBits()
1752 unsigned Opc = ISD::SHL; in SimplifyDemandedBits()
1773 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
1775 ISD::SHL, dl, InnerVT, InnerOp, in SimplifyDemandedBits()
1801 Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA)); in SimplifyDemandedBits()
1830 SDValue NewOp = TLO.DAG.getNode(ISD::SHL, dl, VT, DemandedOp0, Op1); in SimplifyDemandedBits()
1847 isTypeDesirableForOp(ISD::SHL, SmallVT) && in SimplifyDemandedBits()
[all …]
H A DDAGCombiner.cpp1094 ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::MUL) && in reassociationCanBreakAddressingModePattern()
1101 (N1.getOpcode() == ISD::SHL in reassociationCanBreakAddressingModePattern()
1885 case ISD::SHL: return visitSHL(N); in visit()
2034 case ISD::SHL: in combine()
2451 if ((BinOpcode == ISD::SHL || BinOpcode == ISD::SRA || in foldBinOpIntoSelect()
3145 DAG.getNode(ISD::SHL, DL, VT, Y, N)); in visitADDLikeCommutative()
4082 if (N1.getOpcode() == ISD::SHL) { in visitSUB()
4375 return Matcher.getNode(ISD::SHL, DL, VT, N0, Trunc); in visitMUL()
4387 Matcher.getNode(ISD::SHL, DL, VT, N0, in visitMUL()
4445 DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT)); in visitMUL()
[all …]
H A DLegalizeVectorOps.cpp362 case ISD::SHL: in LegalizeOp()
1204 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) in ExpandSEXTINREG()
1214 SDValue Op = DAG.getNode(ISD::SHL, DL, VT, Node->getOperand(0), ShiftSz); in ExpandSEXTINREG()
1272 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
1344 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) && in ExpandBSWAP()
1382 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) && in ExpandBITREVERSE()
1399 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) && in ExpandBITREVERSE()
/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha512-ppc.pl54 $SHL="sldi";
62 $SHL="slwi";
203 $SHL $num,$num,`log(16*$SZ)/log(2)`
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp126 setOperationAction(ISD::SHL, MVT::i32, Custom); in LoongArchTargetLowering()
264 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); in LoongArchTargetLowering()
311 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); in LoongArchTargetLowering()
2546 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in lowerShiftLeftParts()
2550 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in lowerShiftLeftParts()
2552 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusGRLen); in lowerShiftLeftParts()
2598 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One); in lowerShiftRightParts()
2600 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, GRLenMinus1Shamt); in lowerShiftRightParts()
2626 case ISD::SHL: in getLoongArchWOpcode()
2826 case ISD::SHL: in ReplaceNodeResults()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp518 ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL}); in MipsTargetLowering()
834 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { in performANDCombine()
900 And1.getOperand(0).getOpcode() == ISD::SHL) { in performORCombine()
1190 case ISD::SHL: in PerformDAGCombine()
1219 assert(((N->getOpcode() == ISD::SHL && in shouldFoldConstantShiftPairToMask()
1222 N->getOperand(0).getOpcode() == ISD::SHL)) && in shouldFoldConstantShiftPairToMask()
2378 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); in lowerFCOPYSIGN32()
2381 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); in lowerFCOPYSIGN32()
2428 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); in lowerFCOPYSIGN64()
2438 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, in lowerFCOPYSIGN64()
[all …]
H A DMipsISelLowering.h465 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst); in getAddrNonPICSym64()
468 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst); in getAddrNonPICSym64()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp659 case ISD::SHL: in getShiftTypeForNode()
673 assert(V.getOpcode() == ISD::SHL && "invalid opcode"); in isWorthFoldingSHL()
709 if (V.getOpcode() == ISD::SHL && isWorthFoldingSHL(V)) in isWorthFoldingAddr()
714 if (LHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(LHS)) in isWorthFoldingAddr()
716 if (RHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(RHS)) in isWorthFoldingAddr()
739 if (LHSOpcode != ISD::SHL && LHSOpcode != ISD::SRL && LHSOpcode != ISD::SRA) in SelectShiftedRegisterFromAnd()
760 if (LHSOpcode == ISD::SHL) { in SelectShiftedRegisterFromAnd()
868 if (LSL && Subtarget->hasALULSLFast() && V.getOpcode() == ISD::SHL && in isWorthFoldingALU()
943 if (N.getOpcode() == ISD::SHL) { in SelectArithExtendedRegister()
996 if (N.getOpcode() != ISD::SHL) in SelectArithUXTXRegister()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def104 ADD_BINARY_VVP_OP_COMPACT(SHL) REGISTER_PACKED(VVP_SHL)
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1063 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1075 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1079 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1165 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1169 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); in LowerSTORE()
1173 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift); in LowerSTORE()
1293 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()

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