Lines Matching refs:SHL
204 setOperationAction(ISD::SHL, VT, Custom); in addTypeForNEON()
267 setOperationAction(ISD::SHL, VT, Custom); in addMVEVectorTypes()
1009 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT, in ARMTargetLowering()
1188 setOperationAction(ISD::SHL, MVT::i64, Custom); in ARMTargetLowering()
1608 setTargetDAGCombine(ISD::SHL); in ARMTargetLowering()
2022 if (Op.getOpcode() != ISD::SHL) in isSHL16()
3660 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex, in LowerGlobalTLSAddressWindows()
4139 SDValue SHL = in LowerINTRINSIC_WO_CHAIN() local
4140 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy)); in LowerINTRINSIC_WO_CHAIN()
4142 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy)); in LowerINTRINSIC_WO_CHAIN()
4158 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1); in LowerINTRINSIC_WO_CHAIN()
4826 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt); in getARMCmp()
4838 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL && in getARMCmp()
6341 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); in LowerShiftRightParts()
6381 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerShiftLeftParts()
6386 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerShiftLeftParts()
6394 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); in LowerShiftLeftParts()
6446 RMValue = DAG.getNode(ISD::SHL, DL, MVT::i32, RMValue, in LowerSET_ROUNDING()
6675 if (N->getOpcode() == ISD::SHL) { in LowerShift()
6713 N->getOpcode() == ISD::SHL) && in Expand64BitShift()
6757 if (!isOneConstant(N->getOperand(1)) || N->getOpcode() == ISD::SHL) in Expand64BitShift()
10602 case ISD::SHL: in LowerOperation()
10740 case ISD::SHL: in ReplaceNodeResults()
13802 assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA || in isDesirableToCommuteWithShift()
13809 if (N->getOpcode() != ISD::SHL) in isDesirableToCommuteWithShift()
13816 if (N->getOpcode() != ISD::SHL) in isDesirableToCommuteWithShift()
13842 (N->getOperand(0).getOpcode() == ISD::SHL || in isDesirableToCommuteXorWithShift()
13854 if (N->getOperand(0).getOpcode() == ISD::SHL) in isDesirableToCommuteXorWithShift()
13865 assert(((N->getOpcode() == ISD::SHL && in shouldFoldConstantShiftPairToMask()
13868 N->getOperand(0).getOpcode() == ISD::SHL)) && in shouldFoldConstantShiftPairToMask()
13960 if (U->getOperand(0).getOpcode() == ISD::SHL || in PerformSHLSimplify()
13961 U->getOperand(1).getOpcode() == ISD::SHL) in PerformSHLSimplify()
13971 if (N->getOperand(0).getOpcode() != ISD::SHL) in PerformSHLSimplify()
13974 SDValue SHL = N->getOperand(0); in PerformSHLSimplify() local
13977 auto *C2 = dyn_cast<ConstantSDNode>(SHL.getOperand(1)); in PerformSHLSimplify()
14007 SDValue X = SHL.getOperand(0); in PerformSHLSimplify()
14011 SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1)); in PerformSHLSimplify()
14013 LLVM_DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump(); in PerformSHLSimplify()
14014 SHL.dump(); N->dump()); in PerformSHLSimplify()
14253 DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
14260 DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
14273 DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
14281 DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
14292 Res = DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
14323 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL) in CombineANDShift()
14326 bool LeftShift = N0->getOpcode() == ISD::SHL; in CombineANDShift()
14354 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift() local
14356 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL, in CombineANDShift()
14365 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift() local
14367 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL, in CombineANDShift()
14378 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift() local
14380 return DAG.getNode(ISD::SRL, DL, MVT::i32, SHL, in CombineANDShift()
14391 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift() local
14393 return DAG.getNode(ISD::SHL, DL, MVT::i32, SHL, in CombineANDShift()
14405 return DAG.getNode(ISD::SHL, DL, MVT::i32, And, in CombineANDShift()
14471 SDValue SHL = OR->getOperand(1); in PerformORCombineToSMULWBT() local
14473 if (SRL.getOpcode() != ISD::SRL || SHL.getOpcode() != ISD::SHL) { in PerformORCombineToSMULWBT()
14475 SHL = OR->getOperand(0); in PerformORCombineToSMULWBT()
14477 if (!isSRL16(SRL) || !isSHL16(SHL)) in PerformORCombineToSMULWBT()
14482 if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) || in PerformORCombineToSMULWBT()
14488 SHL.getOperand(0) != SDValue(SMULLOHI, 1)) in PerformORCombineToSMULWBT()
14626 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && in PerformORCombineToBFI()
17727 if (ST->isThumb1Only() && N->getOpcode() == ISD::SHL && VT == MVT::i32 && in PerformShiftCombine()
17752 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in PerformShiftCombine() local
17755 ISD::SRL, DL, MVT::i32, SHL, in PerformShiftCombine()
17773 case ISD::SHL: in PerformShiftCombine()
18548 Res = DAG.getNode(ISD::SHL, dl, VT, Res, in PerformCMOVCombine()
18925 case ISD::SHL: in PerformDAGCombine()
19444 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM)) in isVectorLoadExtDesirable()
20296 ISD::SHL, SDLoc(Op), MVT::i32, Op.getOperand(1), in SimplifyDemandedBitsForTargetNode()