Lines Matching refs:SHL
375 { ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
378 { ISD::SHL, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
381 { ISD::SHL, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
393 { ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
396 { ISD::SHL, MVT::v32i8, { 1, 8, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
399 { ISD::SHL, MVT::v64i8, { 1, 8, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
403 { ISD::SHL, MVT::v16i16, { 1, 1, 1, 1 } }, // psllw in getArithmeticInstrCost()
406 { ISD::SHL, MVT::v32i16, { 1, 1, 1, 1 } }, // psllw in getArithmeticInstrCost()
418 { ISD::SHL, MVT::v64i8, { 2, 12, 5, 6 } }, // psllw + pand. in getArithmeticInstrCost()
422 { ISD::SHL, MVT::v16i16, { 2, 7, 4, 4 } }, // psllw + split. in getArithmeticInstrCost()
426 { ISD::SHL, MVT::v8i32, { 1, 1, 1, 1 } }, // pslld in getArithmeticInstrCost()
429 { ISD::SHL, MVT::v16i32, { 1, 1, 1, 1 } }, // pslld in getArithmeticInstrCost()
434 { ISD::SHL, MVT::v4i64, { 1, 1, 1, 1 } }, // psllq in getArithmeticInstrCost()
437 { ISD::SHL, MVT::v8i64, { 1, 1, 1, 1 } }, // psllq in getArithmeticInstrCost()
454 { ISD::SHL, MVT::v16i8, { 1, 8, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
457 { ISD::SHL, MVT::v32i8, { 2, 8, 2, 4 } }, // psllw + pand. in getArithmeticInstrCost()
461 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw in getArithmeticInstrCost()
464 { ISD::SHL, MVT::v16i16,{ 2, 2, 1, 2 } }, // psllw in getArithmeticInstrCost()
468 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld in getArithmeticInstrCost()
471 { ISD::SHL, MVT::v8i32, { 2, 2, 1, 2 } }, // pslld in getArithmeticInstrCost()
475 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } }, // psllq in getArithmeticInstrCost()
478 { ISD::SHL, MVT::v4i64, { 2, 2, 1, 2 } }, // psllq in getArithmeticInstrCost()
495 { ISD::SHL, MVT::v16i8, { 2, 7, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
498 { ISD::SHL, MVT::v32i8, { 4, 7, 7, 8 } }, // 2*(psllw + pand) + split. in getArithmeticInstrCost()
502 { ISD::SHL, MVT::v8i16, { 1, 2, 1, 1 } }, // psllw. in getArithmeticInstrCost()
505 { ISD::SHL, MVT::v16i16,{ 3, 6, 4, 5 } }, // psllw + split. in getArithmeticInstrCost()
509 { ISD::SHL, MVT::v4i32, { 1, 2, 1, 1 } }, // pslld. in getArithmeticInstrCost()
512 { ISD::SHL, MVT::v8i32, { 3, 6, 4, 5 } }, // pslld + split. in getArithmeticInstrCost()
516 { ISD::SHL, MVT::v2i64, { 1, 2, 1, 1 } }, // psllq. in getArithmeticInstrCost()
519 { ISD::SHL, MVT::v4i64, { 3, 6, 4, 5 } }, // 2 x psllq + split. in getArithmeticInstrCost()
538 { ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
542 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw. in getArithmeticInstrCost()
546 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, // pslld in getArithmeticInstrCost()
550 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } }, // psllq. in getArithmeticInstrCost()
687 { ISD::SHL, MVT::v16i8, { 3, 5, 5, 7 } }, // psllw + pand. in getArithmeticInstrCost()
690 { ISD::SHL, MVT::v32i8, { 4, 7, 6, 8 } }, // psllw + pand. in getArithmeticInstrCost()
693 { ISD::SHL, MVT::v64i8, { 4, 7, 6, 8 } }, // psllw + pand. in getArithmeticInstrCost()
697 { ISD::SHL, MVT::v32i16, { 2, 4, 2, 3 } }, // psllw in getArithmeticInstrCost()
709 { ISD::SHL, MVT::v32i16, { 5,10, 5, 7 } }, // psllw + split. in getArithmeticInstrCost()
713 { ISD::SHL, MVT::v16i32, { 2, 4, 2, 3 } }, // pslld in getArithmeticInstrCost()
718 { ISD::SHL, MVT::v4i64, { 1, 4, 1, 2 } }, // psllq in getArithmeticInstrCost()
721 { ISD::SHL, MVT::v8i64, { 1, 4, 1, 2 } }, // psllq in getArithmeticInstrCost()
734 { ISD::SHL, MVT::v16i8, { 3, 5, 5, 7 } }, // psllw + pand. in getArithmeticInstrCost()
737 { ISD::SHL, MVT::v32i8, { 4, 7, 6, 8 } }, // psllw + pand. in getArithmeticInstrCost()
741 { ISD::SHL, MVT::v8i16, { 1, 2, 1, 2 } }, // psllw. in getArithmeticInstrCost()
744 { ISD::SHL, MVT::v16i16, { 2, 4, 2, 3 } }, // psllw. in getArithmeticInstrCost()
748 { ISD::SHL, MVT::v4i32, { 1, 2, 1, 2 } }, // pslld in getArithmeticInstrCost()
751 { ISD::SHL, MVT::v8i32, { 2, 4, 2, 3 } }, // pslld in getArithmeticInstrCost()
755 { ISD::SHL, MVT::v2i64, { 1, 2, 1, 2 } }, // psllq in getArithmeticInstrCost()
758 { ISD::SHL, MVT::v4i64, { 2, 4, 1, 2 } }, // psllq in getArithmeticInstrCost()
770 { ISD::SHL, MVT::v16i8, { 4, 4, 6, 8 } }, // psllw + pand. in getArithmeticInstrCost()
773 { ISD::SHL, MVT::v32i8, { 7, 8,11,14 } }, // psllw + pand + split. in getArithmeticInstrCost()
777 { ISD::SHL, MVT::v8i16, { 1, 3, 1, 2 } }, // psllw. in getArithmeticInstrCost()
780 { ISD::SHL, MVT::v16i16, { 3, 7, 5, 7 } }, // psllw + split. in getArithmeticInstrCost()
784 { ISD::SHL, MVT::v4i32, { 1, 3, 1, 2 } }, // pslld. in getArithmeticInstrCost()
787 { ISD::SHL, MVT::v8i32, { 3, 7, 5, 7 } }, // pslld + split. in getArithmeticInstrCost()
791 { ISD::SHL, MVT::v2i64, { 1, 3, 1, 2 } }, // psllq. in getArithmeticInstrCost()
794 { ISD::SHL, MVT::v4i64, { 3, 7, 4, 6 } }, // psllq + split. in getArithmeticInstrCost()
809 { ISD::SHL, MVT::v16i8, { 9, 10, 6, 9 } }, // psllw + pand. in getArithmeticInstrCost()
813 { ISD::SHL, MVT::v8i16, { 2, 2, 1, 2 } }, // psllw. in getArithmeticInstrCost()
817 { ISD::SHL, MVT::v4i32, { 2, 2, 1, 2 } }, // pslld in getArithmeticInstrCost()
821 { ISD::SHL, MVT::v2i64, { 2, 2, 1, 2 } }, // psllq. in getArithmeticInstrCost()
846 { ISD::SHL, MVT::v16i8, { 4, 8, 4, 5 } }, // extend/vpsllvw/pack sequence. in getArithmeticInstrCost()
849 { ISD::SHL, MVT::v32i8, { 4, 23,11,16 } }, // extend/vpsllvw/pack sequence. in getArithmeticInstrCost()
852 { ISD::SHL, MVT::v64i8, { 6, 19,13,15 } }, // extend/vpsllvw/pack sequence. in getArithmeticInstrCost()
856 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // vpsllvw in getArithmeticInstrCost()
859 { ISD::SHL, MVT::v16i16, { 1, 1, 1, 1 } }, // vpsllvw in getArithmeticInstrCost()
862 { ISD::SHL, MVT::v32i16, { 1, 1, 1, 1 } }, // vpsllvw in getArithmeticInstrCost()
895 { ISD::SHL, MVT::v64i8, { 15, 19,27,33 } }, // vpblendv+split sequence. in getArithmeticInstrCost()
899 { ISD::SHL, MVT::v32i16, { 11, 16,11,15 } }, // 2*extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
903 { ISD::SHL, MVT::v4i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
906 { ISD::SHL, MVT::v8i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
909 { ISD::SHL, MVT::v16i32, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
913 { ISD::SHL, MVT::v2i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
916 { ISD::SHL, MVT::v4i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
919 { ISD::SHL, MVT::v8i64, { 1, 1, 1, 1 } }, in getArithmeticInstrCost()
991 { ISD::SHL, MVT::v4i32, { 2, 3, 1, 3 } }, // vpsllvd (Haswell from agner.org) in getArithmeticInstrCost()
994 { ISD::SHL, MVT::v8i32, { 4, 4, 1, 3 } }, // vpsllvd (Haswell from agner.org) in getArithmeticInstrCost()
997 { ISD::SHL, MVT::v2i64, { 2, 3, 1, 1 } }, // vpsllvq (Haswell from agner.org) in getArithmeticInstrCost()
999 { ISD::SHL, MVT::v4i64, { 4, 4, 1, 2 } }, // vpsllvq (Haswell from agner.org) in getArithmeticInstrCost()
1004 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && Op2Info.isConstant()) in getArithmeticInstrCost()
1013 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && in getArithmeticInstrCost()
1027 { ISD::SHL, MVT::v16i8, { 1, 3, 1, 1 } }, in getArithmeticInstrCost()
1030 { ISD::SHL, MVT::v8i16, { 1, 3, 1, 1 } }, in getArithmeticInstrCost()
1033 { ISD::SHL, MVT::v4i32, { 1, 3, 1, 1 } }, in getArithmeticInstrCost()
1036 { ISD::SHL, MVT::v2i64, { 1, 3, 1, 1 } }, in getArithmeticInstrCost()
1040 { ISD::SHL, MVT::v32i8, { 4, 7, 5, 6 } }, in getArithmeticInstrCost()
1043 { ISD::SHL, MVT::v16i16, { 4, 7, 5, 6 } }, in getArithmeticInstrCost()
1046 { ISD::SHL, MVT::v8i32, { 4, 7, 5, 6 } }, in getArithmeticInstrCost()
1049 { ISD::SHL, MVT::v4i64, { 4, 7, 5, 6 } }, in getArithmeticInstrCost()
1060 ShiftISD = ISD::SHL; in getArithmeticInstrCost()
1067 if (ISD == ISD::SHL && !Op2Info.isUniform() && Op2Info.isConstant()) { in getArithmeticInstrCost()
1118 { ISD::SHL, MVT::v16i8, { 6, 21,11,16 } }, // vpblendvb sequence. in getArithmeticInstrCost()
1119 { ISD::SHL, MVT::v32i8, { 6, 23,11,22 } }, // vpblendvb sequence. in getArithmeticInstrCost()
1120 { ISD::SHL, MVT::v8i16, { 5, 18, 5,10 } }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
1121 { ISD::SHL, MVT::v16i16, { 8, 10,10,14 } }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
1229 { ISD::SHL, MVT::v16i8, { 10, 21,11,17 } }, // pblendvb sequence. in getArithmeticInstrCost()
1230 { ISD::SHL, MVT::v32i8, { 22, 22,27,40 } }, // pblendvb sequence + split. in getArithmeticInstrCost()
1231 { ISD::SHL, MVT::v8i16, { 6, 9,11,11 } }, // pblendvb sequence. in getArithmeticInstrCost()
1232 { ISD::SHL, MVT::v16i16, { 13, 16,24,25 } }, // pblendvb sequence + split. in getArithmeticInstrCost()
1233 { ISD::SHL, MVT::v4i32, { 3, 11, 4, 6 } }, // pslld/paddd/cvttps2dq/pmulld in getArithmeticInstrCost()
1234 { ISD::SHL, MVT::v8i32, { 9, 11,12,17 } }, // pslld/paddd/cvttps2dq/pmulld + split in getArithmeticInstrCost()
1235 { ISD::SHL, MVT::v2i64, { 2, 4, 4, 6 } }, // Shift each lane + blend. in getArithmeticInstrCost()
1236 { ISD::SHL, MVT::v4i64, { 6, 7,11,15 } }, // Shift each lane + blend + split. in getArithmeticInstrCost()
1323 { ISD::SHL, MVT::v16i8, { 15, 24,17,22 } }, // pblendvb sequence. in getArithmeticInstrCost()
1324 { ISD::SHL, MVT::v8i16, { 11, 14,11,11 } }, // pblendvb sequence. in getArithmeticInstrCost()
1325 { ISD::SHL, MVT::v4i32, { 14, 20, 4,10 } }, // pslld/paddd/cvttps2dq/pmulld in getArithmeticInstrCost()
1357 { ISD::SHL, MVT::v16i8, { 13, 21,26,28 } }, // cmpgtb sequence. in getArithmeticInstrCost()
1358 { ISD::SHL, MVT::v8i16, { 24, 27,16,20 } }, // cmpgtw sequence. in getArithmeticInstrCost()
1359 { ISD::SHL, MVT::v4i32, { 17, 19,10,12 } }, // pslld/paddd/cvttps2dq/pmuludq. in getArithmeticInstrCost()
1360 { ISD::SHL, MVT::v2i64, { 4, 6, 5, 7 } }, // splat+shuffle sequence. in getArithmeticInstrCost()