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Searched refs:SEW (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVTargetParser.h72 inline static bool isValidSEW(unsigned SEW) { in isValidSEW() argument
73 return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 64; in isValidSEW()
81 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
103 inline static unsigned encodeSEW(unsigned SEW) { in encodeSEW() argument
104 assert(isValidSEW(SEW) && "Unexpected SEW value"); in encodeSEW()
105 return Log2_32(SEW) - 3; in encodeSEW()
119 unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
122 getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVTargetParser.cpp159 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, in encodeVTYPE() argument
161 assert(isValidSEW(SEW) && "Invalid SEW"); in encodeVTYPE()
163 unsigned VSEWBits = encodeSEW(SEW); in encodeVTYPE()
214 unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) { in getSEWLMULRatio() argument
222 assert(SEW >= 8 && "Unexpected SEW value"); in getSEWLMULRatio()
223 return (SEW * 8) / LMul; in getSEWLMULRatio()
227 getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) { in getSameRatioLMUL() argument
228 unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL); in getSameRatioLMUL()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp216 } SEW = SEWNone; member
228 return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy; in usedVTYPE()
238 SEW = SEWEqual; in demandVTYPE()
262 SEW = std::max(SEW, B.SEW); in doUnion()
282 switch (SEW) { in print()
336 switch (Used.SEW) { in areCompatibleVTYPEs()
422 Res.SEW = DemandedFields::SEWNone; in getDemanded()
437 Res.SEW = DemandedFields::SEWNone; in getDemanded()
454 Res.SEW = DemandedFields::SEWGreaterThanOrEqualAndLessThan64; in getDemanded()
456 Res.SEW = DemandedFields::SEWGreaterThanOrEqual; in getDemanded()
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H A DRISCVVectorPeephole.cpp112 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; in convertToVLMAX() local
113 assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW"); in convertToVLMAX()
114 assert(8 * LMULFixed / SEW > 0); in convertToVLMAX()
123 if (ScaleFixed != 8 * LMULFixed / SEW) in convertToVLMAX()
H A DRISCVInstrInfo.cpp242 // If SEW is different, return false. in isConvertibleToVMV_V_V()
427 MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW in copyPhysRegVector()
1727 // SEW in areRVVInstsReassociable()
2492 ErrInfo = "VL operand w/o SEW operand?"; in verifyInstruction()
2499 ErrInfo = "SEW value expected to be an immediate"; in verifyInstruction()
2504 ErrInfo = "Unexpected SEW value"; in verifyInstruction()
2507 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; in verifyInstruction() local
2508 if (!RISCVVType::isValidSEW(SEW)) { in verifyInstruction()
2509 ErrInfo = "Unexpected SEW value"; in verifyInstruction()
2995 // Print the full VType operand of vsetvli/vsetivli instructions, and the SEW in createMIROperandComment()
3000 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; createMIROperandComment() local
3083 CASE_VFMA_OPCODE_COMMON(OP,TYPE,LMUL,SEW) global() argument
3086 CASE_VFMA_OPCODE_LMULS_M1(OP,TYPE,SEW) global() argument
3092 CASE_VFMA_OPCODE_LMULS_MF2(OP,TYPE,SEW) global() argument
3096 CASE_VFMA_OPCODE_LMULS_MF4(OP,TYPE,SEW) global() argument
3303 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP,NEWOP,TYPE,LMUL,SEW) global() argument
3308 CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP,NEWOP,TYPE,SEW) global() argument
3314 CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP,NEWOP,TYPE,SEW) global() argument
3323 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP,NEWOP,TYPE,SEW) global() argument
3327 CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP,NEWOP,TYPE,SEW) global() argument
3505 CASE_FP_WIDEOP_OPCODE_COMMON(OP,LMUL,SEW) global() argument
3519 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP,LMUL,SEW) global() argument
[all...]
H A DRISCVInstrInfoVSDPatterns.td257 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW,
273 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW,
405 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW)
436 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_E"#ivti.SEW)
465 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW)
616 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW)
629 … (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
640 … (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
661 (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_E"#vti.SEW#"_TIED")
672 … (!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
[all …]
H A DRISCVInstrInfoVPseudos.td40 /// SEW - Some instructions have semantics which depend on SEW. This is
197 int SEW = sew;
259 int SEW = Sew;
374 // This functor is used to obtain the int vector type that has the same SEW and
387 // {SEW, VLMul} values set a valid VType to deal with this mask type.
388 // we assume SEW=1 and set corresponding LMUL. vsetvli insertion will
389 // look for SEW=1 to optimize based on surrounding instructions.
390 int SEW = 1;
401 // vbool<n>_t, <n> = SEW/LMU
[all...]
H A DRISCVInstrInfoVVLPatterns.td1085 … instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK",
1104 … instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK",
1324 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
1342 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
1410 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_E"#ivti.SEW#"_MASK")
1484 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
1503 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
1511 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1");
1517 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")
1528 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1");
[all …]
H A DRISCVSchedSiFive7.td13 /// and the worst case sew is the smallest SEW for that LMUL.
21 /// and the worst case sew is the smallest SEW for that LMUL.
90 // formula vl * ceil((SEW * nf) / DLEN), where SEW * nf is the segment size.
94 // (VLEN * LMUL) / SEW
114 // c = ceil(VLEN / SEW) * LMUL
132 // TODO: Add SchedSEWSetFP upstream and remove the SEW=8 case.
140 /// Cycles for reductions take approximately VL*SEW/DLEN + 5(4 + log(DLEN/SEW))
143 // VLUpperBound*SEW/DLEN is equivalent to 2*LMUL since
144 // VLUpperBound=(VLEN*LMUL)/SEW.
165 // (VLEN * LMUL) / SEW
[all …]
H A DRISCVInstrInfoZvk.td195 defvar I32IntegerVectors = !filter(vti, AllIntegerVectors, !eq(vti.SEW, 32));
197 !or(!eq(vti.SEW, 32), !eq(vti.SEW, 64)));
621 // Invert the immediate and mask it to SEW for readability.
649 (!cast<SDNodeXForm>("InvRot" # vti.SEW # "Imm") uimm6:$rs1),
766 (!cast<SDNodeXForm>("InvRot" # vti.SEW # "Imm") uimm6:$rs1),
976 instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,
989 !if(isSEWAware, instruction#"_VI_"#vti.LMul.MX#"_E"#vti.SEW,
1003 !if(isSEWAware, instruction#"_VI_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK",
H A DRISCVISelDAGToDAG.cpp567 unsigned SEW = in selectVSETVLI() local
572 unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, SEW, /*TailAgnostic*/ true, in selectVSETVLI()
580 if (*VLEN / RISCVVType::getSEWLMULRatio(SEW, VLMul) == C->getZExtValue()) in selectVSETVLI()
1638 SDValue SEW = CurDAG->getTargetConstant( in Select() local
1645 ReplaceNode(Node, CurDAG->getMachineNode(VMSetOpcode, DL, VT, VL, SEW)); in Select()
1652 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1655 {Cmp, Cmp, VL, SEW})); in Select()
1717 SDValue SEW = CurDAG->getTargetConstant( in Select() local
1744 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1764 {MaskedOff, Src1, Src2, V0, VL, SEW, Glue}), in Select()
[all …]
H A DRISCVInstrInfoXSf.td790 if !ne(vti.SEW, 8) then {
791 defvar finfo = GetFTypeInfo<vti.SEW>;
806 if !ne(vti.SEW, 8) then {
807 defvar finfo = GetFTypeInfo<vti.SEW>;
H A DRISCVScheduleV.td32 // For floating-point instructions, SEW won't be 8.
34 // For widening instructions, SEW will not be 64.
45 // Helper function to get the smallest SEW that can be used with LMUL mx
151 // ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
H A DRISCVSchedSiFiveP600.td13 /// and the worst case sew is the smallest SEW for that LMUL.
443 // Worst case needs 64 cycles if SEW is equal to 64.
583 // Worst case needs 76 cycles if SEW is equal to 64.
H A DRISCVISelLowering.cpp2707 // each fractional LMUL we support SEW between 8 and LMUL*ELEN. in getContainerForFixedLengthVector()
4809 // twice the SEW (Hence the restriction on not using the maximum in getWideningInterleave()
5135 // If this is SEW=64 on RV32, use a strided load with a stride of x0. in lowerVECTOR_SHUFFLE()
8077 // Custom-lower a SPLAT_VECTOR_PARTS where XLEN<SEW, as the SEW element type is
8244 // RVV only has truncates which operate from SEW*2->SEW, so lower arbitrary in lowerVectorTruncLike()
8813 // that a widening operation never uses SEW=64. in lowerVectorIntrinsicScalars()
8824 // instruction to sign-extend since SEW>XLEN. in lowerVectorIntrinsicScalars()
8846 // Double the VL since we halved SEW in lowerVectorIntrinsicScalars()
8861 SDValue SEW = DAG.getConstant(Sew, DL, XLenVT); lowerVectorIntrinsicScalars() local
8876 SDValue SEW = DAG.getConstant(Sew, DL, XLenVT); lowerVectorIntrinsicScalars() local
17928 unsigned SEW = RISCVVType::decodeVSEW(VSEW); computeKnownBitsForTargetNode() local
18541 lookupMaskedIntrinsic(uint16_t MCOpcode,RISCVII::VLMUL LMul,unsigned SEW) lookupMaskedIntrinsic() argument
[all...]
H A DRISCVInstrInfoV.td120 // The scheudling resources are relevant to LMUL and may be relevant to SEW.
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp142 unsigned SEW = RISCVVType::getSEW(VTypeI); in createInstruments() local
144 switch (SEW) { in createInstruments()
169 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL() argument
202 auto EMUL = RISCVVType::getSameRatioLMUL(SEW, LMUL, EEW); in getEEWAndEMUL()
248 uint8_t SEW = SI ? SI->getSEW() : 0; in getSchedClassID() local
253 auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW); in getSchedClassID()
257 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW); in getSchedClassID()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector.td611 // vsetvl/vsetvlmax are a macro because they require constant integers in SEW
1208 // Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW
1212 // Widening signed integer add/subtract, 2*SEW = SEW +/- SEW
1215 // Widening unsigned integer add/subtract, 2*SEW = 2*SEW +/- SEW
1218 // Widening signed integer add/subtract, 2*SEW = 2*SEW +/- SEW
1562 // Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW
1577 // Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW
1634 // Widening FP add/subtract, 2*SEW = SEW +/- SEW
1646 // Widening FP add/subtract, 2*SEW = SEW +/- SEW
2328 // Reinterpret between different type under the same SEW and LMUL
[all …]
H A DRISCVVTypes.def32 // - ElBits is the size of one element in bits (SEW).
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.h46 uint8_t SEW; member
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGDebugInfo.cpp811 unsigned SEW = CGM.getContext().getTypeSize(Info.ElementType); in CreateType() local
815 unsigned FixedSize = ElementCount * SEW; in CreateType()
836 SEW / 8, // SEW is in bits. in CreateType()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp1841 uint64_t SEW = RISCVVType::decodeVSEW( in computeKnownBitsFromOperator() local
1847 uint64_t MaxVL = MaxVLEN / RISCVVType::getSEWLMULRatio(SEW, VLMUL); in computeKnownBitsFromOperator()
/freebsd/share/misc/
H A Dusb_vendors5651 5b11 SEW-2001u Card
5725 7011 SEW-2003U Card