106c3fb27SDimitry Andric //===-- RISCVMCTargetDesc.h - RISC-V Target Descriptions --------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 906c3fb27SDimitry Andric // This file provides RISC-V specific target descriptions. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "llvm/MC/MCTargetOptions.h" 170b57cec5SDimitry Andric #include "llvm/Support/DataTypes.h" 180b57cec5SDimitry Andric #include <memory> 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric namespace llvm { 210b57cec5SDimitry Andric class MCAsmBackend; 220b57cec5SDimitry Andric class MCCodeEmitter; 230b57cec5SDimitry Andric class MCContext; 240b57cec5SDimitry Andric class MCInstrInfo; 250b57cec5SDimitry Andric class MCObjectTargetWriter; 260b57cec5SDimitry Andric class MCRegisterInfo; 270b57cec5SDimitry Andric class MCSubtargetInfo; 280b57cec5SDimitry Andric class Target; 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII, 310b57cec5SDimitry Andric MCContext &Ctx); 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, 340b57cec5SDimitry Andric const MCRegisterInfo &MRI, 350b57cec5SDimitry Andric const MCTargetOptions &Options); 360b57cec5SDimitry Andric 370b57cec5SDimitry Andric std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI, 380b57cec5SDimitry Andric bool Is64Bit); 39*0fca6ea1SDimitry Andric 40*0fca6ea1SDimitry Andric namespace RISCVVInversePseudosTable { 41*0fca6ea1SDimitry Andric 42*0fca6ea1SDimitry Andric struct PseudoInfo { 43*0fca6ea1SDimitry Andric uint16_t Pseudo; 44*0fca6ea1SDimitry Andric uint16_t BaseInstr; 45*0fca6ea1SDimitry Andric uint8_t VLMul; 46*0fca6ea1SDimitry Andric uint8_t SEW; 47*0fca6ea1SDimitry Andric }; 48*0fca6ea1SDimitry Andric 49*0fca6ea1SDimitry Andric #define GET_RISCVVInversePseudosTable_DECL 50*0fca6ea1SDimitry Andric #include "RISCVGenSearchableTables.inc" 51*0fca6ea1SDimitry Andric 52*0fca6ea1SDimitry Andric } // namespace RISCVVInversePseudosTable 53*0fca6ea1SDimitry Andric } // namespace llvm 540b57cec5SDimitry Andric 550b57cec5SDimitry Andric // Defines symbolic names for RISC-V registers. 560b57cec5SDimitry Andric #define GET_REGINFO_ENUM 570b57cec5SDimitry Andric #include "RISCVGenRegisterInfo.inc" 580b57cec5SDimitry Andric 590b57cec5SDimitry Andric // Defines symbolic names for RISC-V instructions. 600b57cec5SDimitry Andric #define GET_INSTRINFO_ENUM 61753f127fSDimitry Andric #define GET_INSTRINFO_MC_HELPER_DECLS 620b57cec5SDimitry Andric #include "RISCVGenInstrInfo.inc" 630b57cec5SDimitry Andric 640b57cec5SDimitry Andric #define GET_SUBTARGETINFO_ENUM 650b57cec5SDimitry Andric #include "RISCVGenSubtargetInfo.inc" 660b57cec5SDimitry Andric 670b57cec5SDimitry Andric #endif 68