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Searched refs:RegIdx (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDetectDeadLanes.h57 const VRegInfo &getVRegInfo(unsigned RegIdx) const { in getVRegInfo() argument
58 return VRegInfos[RegIdx]; in getVRegInfo()
61 bool isDefinedByCopy(unsigned RegIdx) const { in isDefinedByCopy() argument
62 return DefinedByCopy.test(RegIdx); in isDefinedByCopy()
101 void PutInWorklist(unsigned RegIdx) { in PutInWorklist() argument
102 if (WorklistMembers.test(RegIdx)) in PutInWorklist()
104 WorklistMembers.set(RegIdx); in PutInWorklist()
105 Worklist.push_back(RegIdx); in PutInWorklist()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp279 unsigned RegIdx = Register::virtReg2Index(Reg); in determineInitialDefinedLanes() local
280 DefinedByCopy.set(RegIdx); in determineInitialDefinedLanes()
281 PutInWorklist(RegIdx); in determineInitialDefinedLanes()
456 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in computeSubRegisterLaneBitInfo() local
457 Register Reg = Register::index2VirtReg(RegIdx); in computeSubRegisterLaneBitInfo()
460 VRegInfo &Info = VRegInfos[RegIdx]; in computeSubRegisterLaneBitInfo()
467 unsigned RegIdx = Worklist.front(); in computeSubRegisterLaneBitInfo() local
469 WorklistMembers.reset(RegIdx); in computeSubRegisterLaneBitInfo()
470 VRegInfo &Info = VRegInfos[RegIdx]; in computeSubRegisterLaneBitInfo()
471 Register Reg = Register::index2VirtReg(RegIdx); in computeSubRegisterLaneBitInfo()
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H A DSplitKit.cpp471 VNInfo *SplitEditor::defValue(unsigned RegIdx, in defValue() argument
478 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defValue()
487 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP)); in defValue()
508 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) { in forceRecompute() argument
509 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)]; in forceRecompute()
521 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false); in forceRecompute()
548 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { in buildCopy() argument
562 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx)); in buildCopy()
592 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, const VNInfo *ParentVNI, in defFromParent() argument
596 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defFromParent()
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H A DSplitKit.h328 /// intervals. Given a pair (RegIdx, ParentVNI->id), Values contains:
330 /// 1. No entry - the value is not mapped to Edit.get(RegIdx).
332 /// Edit.get(RegIdx). Each value is represented by a minimal live range at
334 /// of RegIdx in RegAssign.
346 /// getLICalc - Return the LICalc to use for RegIdx. In spill mode, the
349 LiveIntervalCalc &getLICalc(unsigned RegIdx) {
350 return LICalc[SpillMode != SM_Partition && RegIdx != 0];
361 /// defValue - define a value in RegIdx from ParentVNI at Idx.
369 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx,
372 /// forceRecompute - Force the live range of ParentVNI in RegIdx t
343 getLICalc(unsigned RegIdx) getLICalc() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
247 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
249 if (RegIdx >= RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
H A DARMISelLowering.cpp4542 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); in LowerFormalArguments() local
4543 if (RegIdx != std::size(GPRArgRegs)) in LowerFormalArguments()
4544 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp891 struct RegIdxOp RegIdx; member
906 Op->RegIdx.Index = Index; in CreateReg()
907 Op->RegIdx.RegInfo = RegInfo; in CreateReg()
908 Op->RegIdx.Kind = RegKind; in CreateReg()
909 Op->RegIdx.Tok.Data = Str.data(); in CreateReg()
910 Op->RegIdx.Tok.Length = Str.size(); in CreateReg()
920 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR32Reg()
921 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); in getGPR32Reg()
923 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPR32Reg()
929 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPRMM16Reg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRAsmPrinter.cpp132 unsigned RegIdx = ByteNumber / BytesPerReg; in PrintAsmOperand() local
133 if (RegIdx >= NumOpRegs) in PrintAsmOperand()
135 Reg = MI->getOperand(OpNum + RegIdx).getReg(); in PrintAsmOperand()
H A DAVRISelLowering.cpp1266 unsigned RegIdx = RegLastIdx + TotalBytes; in analyzeArguments() local
1267 RegLastIdx = RegIdx; in analyzeArguments()
1269 if (RegIdx >= RegList8.size()) { in analyzeArguments()
1284 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); in analyzeArguments()
1286 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); in analyzeArguments()
1295 RegIdx -= VT.getStoreSize(); in analyzeArguments()
1349 int RegIdx = TotalBytes - 1; in analyzeReturnValues() local
1354 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); in analyzeReturnValues()
1356 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); in analyzeReturnValues()
1363 RegIdx -= VT.getStoreSize(); in analyzeReturnValues()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp547 int RegIdx = mapRegToGPRIndex(LI.PhysReg); in runOnMachineFunction()
548 if (RegIdx >= 0) in runOnMachineFunction()
549 LOHInfos[RegIdx].OneUser = true; in runOnMachineFunction()
551 int RegIdx = mapRegToGPRIndex(LI.PhysReg); runOnMachineFunction() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp315 unsigned RegIdx = Imm & 0xff; in DECODE_OPERAND_REG_8() local
317 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); in DECODE_OPERAND_REG_8()
326 unsigned RegIdx = Imm & 0x7f; in DecodeVGPR_16_Lo128RegisterClass() local
328 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); in DecodeVGPR_16_Lo128RegisterClass()
340 unsigned RegIdx = Imm & 0x7f; in decodeOperand_VSrcT16_Lo128() local
341 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); in decodeOperand_VSrcT16_Lo128()
356 unsigned RegIdx = Imm & 0xff; in decodeOperand_VSrcT16() local
357 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); in decodeOperand_VSrcT16()
860 unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK; in convertTrue16OpSel() local
861 Op.setReg(ConversionRC.getRegister(RegIdx * 2 + 1)); in convertTrue16OpSel()
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H A DAMDGPUDisassembler.h127 MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { in getMSACtrlReg()
79 uint64_t RegNum = RegIdx->getAsZExtVal(); in getMSACtrlReg()
841 SDValue RegIdx = Node->getOperand(2); in trySelect() local
843 getMSACtrlReg(RegIdx), MVT::i32); in trySelect()
910 SDValue RegIdx = Node->getOperand(2); in trySelect() local
913 getMSACtrlReg(RegIdx), Value); in trySelect()
H A DMipsSEISelDAGToDAG.h33 unsigned getMSACtrlReg(const SDValue RegIdx) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp652 unsigned RegIdx = Encoding & AMDGPU::HWEncoding::REG_IDX_MASK; in getMachineOpValueT16Lo128() local
655 assert((!IsVGPR || isUInt<7>(RegIdx)) && "VGPR0-VGPR127 expected!"); in getMachineOpValueT16Lo128()
656 Op = (IsVGPR ? 0x100 : 0) | (IsHi ? 0x80 : 0) | RegIdx; in getMachineOpValueT16Lo128()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ExpandPseudo.cpp764 for (int64_t OpndIdx = 7, RegIdx = 0; in expandVastartSaveXmmRegs() local
766 OpndIdx++, RegIdx++) { in expandVastartSaveXmmRegs()
770 NewMI.addImm(FrameOffset + VarArgsRegsOffset + RegIdx * 16); in expandVastartSaveXmmRegs()
H A DX86SpeculativeLoadHardening.cpp1867 unsigned RegIdx = Log2_32(RegBytes); in canHardenRegister() local
1868 assert(RegIdx < 4 && "Unsupported register size"); in canHardenRegister()
1880 if (RC == NOREXRegClasses[RegIdx]) in canHardenRegister()
1886 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]); in canHardenRegister()
H A DX86FastISel.cpp2631 unsigned RegIdx = X86::sub_16bit; in fastLowerIntrinsicCall() local
2632 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, RegIdx); in fastLowerIntrinsicCall()
H A DX86InstrInfo.cpp5796 unsigned RegIdx = UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr); in foldImmediateImpl() local
5797 if (RegIdx < 2) in foldImmediateImpl()
5806 UseMI.removeOperand(RegIdx); in foldImmediateImpl()
H A DX86ISelLowering.cpp36476 for (unsigned RegIdx = 0; SavedRegs[RegIdx]; ++RegIdx) { in EmitSjLjDispatchBlock() local
36477 unsigned Reg = SavedRegs[RegIdx]; in EmitSjLjDispatchBlock()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DVarLocBasedImpl.cpp1456 LocIndex RegIdx = LocIndex::fromRawInteger(*It); in collectAllVarLocs() local
1457 Collected.push_back(VarLocIDs[RegIdx]); in collectAllVarLocs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2825 unsigned RegIdx = RegNum / AlignSize; in getRegularReg() local
2834 if (RegIdx >= RC.getNumRegs()) { in getRegularReg()
2839 unsigned Reg = RC.getRegister(RegIdx); in getRegularReg()
4893 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS() local
4894 if (RegIdx & 1) { in validateGWS()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp4773 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); in CC_LoongArch() local
4775 if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1) in CC_LoongArch()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp2297 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs); in allocateVGPR32Input() local
2298 if (RegIdx == ArgVGPRs.size()) { in allocateVGPR32Input()
2305 unsigned Reg = ArgVGPRs[RegIdx]; in allocateVGPR32Input()
2319 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs); in allocateSGPR32InputImpl() local
2320 if (RegIdx == ArgSGPRs.size()) in allocateSGPR32InputImpl()
2323 unsigned Reg = ArgSGPRs[RegIdx]; in allocateSGPR32InputImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp19075 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); in CC_RISCV() local
19077 if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1) in CC_RISCV()