Lines Matching refs:RegIdx
279 unsigned RegIdx = Register::virtReg2Index(Reg); in determineInitialDefinedLanes() local
280 DefinedByCopy.set(RegIdx); in determineInitialDefinedLanes()
281 PutInWorklist(RegIdx); in determineInitialDefinedLanes()
456 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in computeSubRegisterLaneBitInfo() local
457 Register Reg = Register::index2VirtReg(RegIdx); in computeSubRegisterLaneBitInfo()
460 VRegInfo &Info = VRegInfos[RegIdx]; in computeSubRegisterLaneBitInfo()
467 unsigned RegIdx = Worklist.front(); in computeSubRegisterLaneBitInfo() local
469 WorklistMembers.reset(RegIdx); in computeSubRegisterLaneBitInfo()
470 VRegInfo &Info = VRegInfos[RegIdx]; in computeSubRegisterLaneBitInfo()
471 Register Reg = Register::index2VirtReg(RegIdx); in computeSubRegisterLaneBitInfo()
484 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in computeSubRegisterLaneBitInfo()
485 Register Reg = Register::index2VirtReg(RegIdx); in computeSubRegisterLaneBitInfo()
486 const VRegInfo &Info = VRegInfos[RegIdx]; in computeSubRegisterLaneBitInfo()
509 unsigned RegIdx = Register::virtReg2Index(Reg); in modifySubRegisterOperandStatus() local
510 const DeadLaneDetector::VRegInfo &RegInfo = DLD.getVRegInfo(RegIdx); in modifySubRegisterOperandStatus()