315   unsigned RegIdx = Imm & 0xff;  in DECODE_OPERAND_REG_8()  local
317   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));  in DECODE_OPERAND_REG_8()
326   unsigned RegIdx = Imm & 0x7f;  in DecodeVGPR_16_Lo128RegisterClass()  local
328   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));  in DecodeVGPR_16_Lo128RegisterClass()
340     unsigned RegIdx = Imm & 0x7f;  in decodeOperand_VSrcT16_Lo128()  local
341     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));  in decodeOperand_VSrcT16_Lo128()
356     unsigned RegIdx = Imm & 0xff;  in decodeOperand_VSrcT16()  local
357     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));  in decodeOperand_VSrcT16()
860       unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK;  in convertTrue16OpSel()  local
861       Op.setReg(ConversionRC.getRegister(RegIdx * 2 + 1));  in convertTrue16OpSel()
1239 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx,  in createVGPR16Operand()  argument
1241   unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0);  in createVGPR16Operand()