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Searched refs:RO (Results 1 – 25 of 69) sorted by relevance

123

/freebsd/contrib/ntp/libparse/
H A Dinfo_trimble.c56 { CMD_RDATAA, "CMD_RDATAA", "data channel A configuration (0x3D)", "trimble_channelA", RO },
57 { CMD_RALMANAC, "CMD_RALMANAC", "almanac data for sat (0x40)", "gps_almanac", RO },
58 { CMD_RCURTIME, "CMD_RCURTIME", "GPS time (0x41)", "gps_time", RO },
59 …{ CMD_RSPOSXYZ, "CMD_RSPOSXYZ", "single precision XYZ position (0x42)", "gps_position(XYZ)", RO|DE…
60 { CMD_RVELOXYZ, "CMD_RVELOXYZ", "velocity fix (XYZ ECEF) (0x43)", "gps_velocity(XYZ)", RO|DEF },
61 { CMD_RBEST4, "CMD_RBEST4", "best 4 satellite selection (0x44)", "trimble_best4", RO|DEF },
62 { CMD_RVERSION, "CMD_RVERSION", "software version (0x45)", "trimble_version", RO|DEF },
63 …{ CMD_RRECVHEALTH, "CMD_RRECVHEALTH", "receiver health (0x46)", "trimble_receiver_health", RO|DEF …
64 …SIGNALLV, "CMD_RSIGNALLV", "signal levels of all satellites (0x47)", "trimble_signal_levels", RO },
65 { CMD_RMESSAGE, "CMD_RMESSAGE", "GPS system message (0x48)", "gps-message", RO|DEF },
[all …]
/freebsd/contrib/ntp/ntpd/
H A Dntp_control.c340 { CS_STRATUM, RO, "stratum" }, /* 2 */
341 { CS_PRECISION, RO, "precision" }, /* 3 */
342 { CS_ROOTDELAY, RO, "rootdelay" }, /* 4 */
343 { CS_ROOTDISPERSION, RO, "rootdisp" }, /* 5 */
344 { CS_REFID, RO, "refid" }, /* 6 */
345 { CS_REFTIME, RO, "reftime" }, /* 7 */
346 { CS_POLL, RO, "tc" }, /* 8 */
347 { CS_PEERID, RO, "peer" }, /* 9 */
348 { CS_OFFSET, RO, "offset" }, /* 10 */
349 { CS_DRIFT, RO, "frequenc
[all...]
H A Drefclock_neoclock4x.c738 tt = add_var(&out->kv_list, sizeof(tmpbuf)-1, RO|DEF); in neoclock4x_control()
741 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
743 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
745 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
747 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
754 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
761 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
768 tt = add_var(&out->kv_list, 80, RO|DEF); in neoclock4x_control()
770 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
772 tt = add_var(&out->kv_list, 80, RO|DE in neoclock4x_control()
[all...]
H A Drefclock_parse.c3573 tt = add_var(&out->kv_list, 80, RO); in parse_control()
3580 tt = add_var(&out->kv_list, 80, RO|DEF); in parse_control()
3584 start = tt = add_var(&out->kv_list, 128, RO|DEF); in parse_control()
3604 start = tt = add_var(&out->kv_list, 512, RO|DEF); in parse_control()
3638 start = tt = add_var(&out->kv_list, 80, RO|DEF); in parse_control()
3655 start = tt = add_var(&out->kv_list, LEN_STATES, RO|DEF); in parse_control()
3699 tt = add_var(&out->kv_list, 32, RO); in parse_control()
3702 tt = add_var(&out->kv_list, 80, RO); in parse_control()
3705 tt = add_var(&out->kv_list, 128, RO); in parse_control()
4360 set_var(&parse->kv, buffer, strlen(buffer)+1, RO|DEF); in gps16x_message()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td203 class CompactBranchMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
204 InstSE<(outs), (ins RO:$rs, opnd:$offset),
213 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
215 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
217 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
226 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
228 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
230 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
263 class LLBaseMM<string opstr, RegisterOperand RO> :
264 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
[all …]
H A DMipsInstrInfo.td1318 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1321 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1323 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1330 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1334 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1336 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1352 class LogicNOR<string opstr, RegisterOperand RO>:
1353 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1355 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1361 RegisterOperand RO, InstrItinClass itin,
[all …]
H A DMicroMipsDSPInstrInfo.td217 RegisterOperand RO, Operand ImmOpnd> {
218 dag OutOperandList = (outs RO:$rt);
219 dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
221 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
253 InstrItinClass itin, RegisterOperand RO> {
254 dag OutOperandList = (outs RO:$rd);
255 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs);
257 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
325 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
328 dag InOperandList = (ins RO:$ac);
[all …]
H A DMipsDSPInstrInfo.td335 RegisterOperand RO> {
336 dag OutOperandList = (outs RO:$rd);
339 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
345 InstrItinClass itin, RegisterOperand RO> {
346 dag OutOperandList = (outs RO:$rd);
347 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa);
349 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
356 RegisterOperand RO, Operand ImmOpnd> {
357 dag OutOperandList = (outs RO:$rd);
358 dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
[all …]
H A DMips64InstrInfo.td455 class Count1s<string opstr, RegisterOperand RO>:
456 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
457 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
461 class ExtsCins<string opstr, InstrItinClass itin, RegisterOperand RO,
463 InstSE<(outs RO:$rt), (ins RO:$rs, uimm5:$pos, uimm5:$lenm1),
465 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, imm:$lenm1))],
489 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> :
490 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
492 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
500 class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> :
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp2020rdb.dts48 label = "NOR (RO) Vitesse-7385 Firmware";
55 label = "NOR (RO) DTB Image";
62 label = "NOR (RO) Linux Kernel Image";
77 label = "NOR (RO) U-Boot Image";
93 label = "NAND (RO) U-Boot Image";
100 label = "NAND (RO) DTB Image";
107 label = "NAND (RO) Linux Kernel Image";
114 label = "NAND (RO) Compressed RFS Image";
161 label = "SPI (RO) U-Boot Image";
168 label = "SPI (RO) DTB Image";
[all …]
H A Dp1020rdb.dtsi48 label = "NOR (RO) Vitesse-7385 Firmware";
55 label = "NOR (RO) DTB Image";
62 label = "NOR (RO) Linux Kernel Image";
77 label = "NOR (RO) U-Boot Image";
93 label = "NAND (RO) U-Boot Image";
100 label = "NAND (RO) DTB Image";
107 label = "NAND (RO) Linux Kernel Image";
114 label = "NAND (RO) Compressed RFS Image";
H A Dp1021mds.dts42 label = "NAND (RO) U-Boot Image";
49 label = "NAND (RO) DTB Image";
56 label = "NAND (RO) Linux Kernel Image";
63 label = "NAND (RO) Compressed RFS Image";
82 label = "NAND (RO) QE Ucode";
/freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zfs_mount/
H A Dzfs_mount_remount.ksh57 typeset RO="-t zfs -ur"
60 typeset RO="-o remount,ro"
121 log_must mount $RO $TESTFS $MNTPFS
133 log_must mount $RO $TESTSNAP $MNTPSNAP
156 log_must mount $RO $TESTFS/crypt $CRYPT_MNTPFS
/freebsd/sys/dev/aic7xxx/
H A Daic79xx.reg214 access_mode RO
288 access_mode RO
431 access_mode RO
456 access_mode RO
637 access_mode RO
648 access_mode RO
659 access_mode RO
685 access_mode RO
695 access_mode RO
705 access_mode RO
[all …]
H A Daic7xxx.reg106 access_mode RO
279 access_mode RO
312 access_mode RO
328 access_mode RO
344 access_mode RO
421 access_mode RO
631 access_mode RO
637 access_mode RO
649 access_mode RO
656 access_mode RO
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCFIInstrInserter.cpp372 CSRSavedLocation RO = it->second; in insertCFIInstrs() local
373 if (!RO.Reg && RO.Offset) { in insertCFIInstrs()
375 MCCFIInstruction::createOffset(nullptr, Reg, *RO.Offset)); in insertCFIInstrs()
376 } else if (RO.Reg && !RO.Offset) { in insertCFIInstrs()
378 MCCFIInstruction::createRegister(nullptr, Reg, *RO.Reg)); in insertCFIInstrs()
/freebsd/sys/dts/powerpc/
H A Dp1020rdb.dts99 label = "NOR (RO) Vitesse-7385 Firmware";
106 label = "NOR (RO) DTB Image";
113 label = "NOR (RO) Linux Kernel Image";
128 label = "NOR (RO) U-Boot Image";
144 label = "NAND (RO) U-Boot Image";
151 label = "NAND (RO) DTB Image";
158 label = "NAND (RO) Linux Kernel Image";
165 label = "NAND (RO) Compressed RFS Image";
288 label = "SPI (RO) U-Boot Image";
295 label = "SPI (RO) DTB Image";
[all …]
/freebsd/contrib/bsddialog/examples_library/
H A Dform.c17 #define RO BSDDIALOG_FIELDREADONLY macro
25 {"Input:", 1, 0, "read only", 1, 10, 30, 50, NULL, RO, "desc 2"}, in main()
/freebsd/usr.sbin/cron/doc/
H A DMAIL10 Status: RO
28 Status: RO
54 Status: RO
83 Status: RO
95 Status: RO
109 Status: RO
128 Status: RO
157 Status: RO
205 Status: RO
229 Status: RO
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp818 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1); in updatePhiNodes() local
820 SR = RO.getReg(), SSR = RO.getSubReg(); in updatePhiNodes()
822 TR = RO.getReg(), TSR = RO.getSubReg(); in updatePhiNodes()
824 FR = RO.getReg(), FSR = RO.getSubReg(); in updatePhiNodes()
H A DHexagonGenInsert.cpp386 OrderedRegisterList(const RegisterOrdering &RO) in OrderedRegisterList() argument
387 : MaxSize(MaxORLSize), Ord(RO) {} in OrderedRegisterList()
528 void buildOrderingMF(RegisterOrdering &RO) const;
529 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
594 void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const { in buildOrderingMF()
607 RO.insert(std::make_pair(R, Index++)); in buildOrderingMF()
618 RegisterOrdering &RO) const { in buildOrderingBT()
632 RO.insert(std::make_pair(VRs[i], i)); in buildOrderingBT()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86WinCOFFTargetStreamer.cpp352 for (RegSaveOffset RO : RegSaveOffsets) in emitFrameDataRecord() local
353 FuncOS << printFPOReg(MRI, RO.Reg) << ' ' << CFAVar << ' ' << RO.Offset in emitFrameDataRecord()
/freebsd/secure/caroot/trusted/
H A DcertSIGN_ROOT_CA.pem19 Issuer: C = RO, O = certSIGN, OU = certSIGN ROOT CA
23 Subject: C = RO, O = certSIGN, OU = certSIGN ROOT CA
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCodeGenFunction.cpp2807 const MultiVersionResolverOption &RO) { in FormAArch64ResolverCondition() argument
2809 for (const StringRef &Feature : RO.Conditions.Features) in FormAArch64ResolverCondition()
2818 const MultiVersionResolverOption &RO) { in FormX86ResolverCondition() argument
2821 if (!RO.Conditions.Architecture.empty()) { in FormX86ResolverCondition()
2822 StringRef Arch = RO.Conditions.Architecture; in FormX86ResolverCondition()
2831 if (!RO.Conditions.Features.empty()) { in FormX86ResolverCondition()
2832 llvm::Value *FeatureCond = EmitX86CpuSupports(RO.Conditions.Features); in FormX86ResolverCondition()
2892 for (const MultiVersionResolverOption &RO : Options) { in EmitAArch64MultiVersionResolver() local
2894 llvm::Value *Condition = FormAArch64ResolverCondition(RO); in EmitAArch64MultiVersionResolver()
2898 CreateMultiVersionResolverReturn(CGM, Resolver, Builder, RO.Function, in EmitAArch64MultiVersionResolver()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DMCDisassembler.cpp56 SMC_PCASE(RO, 1) in getSMCPriority()

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