1/* 2 * P1020 RDB Device Tree Source 3 * 4 * Copyright 2009 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/dts-v1/; 36 37/ { 38 model = "fsl,P1020"; 39 compatible = "fsl,P1020RDB"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 43 aliases { 44 serial0 = &serial0; 45 serial1 = &serial1; 46 ethernet0 = &enet0; 47 ethernet1 = &enet1; 48 ethernet2 = &enet2; 49 pci0 = &pci0; 50 pci1 = &pci1; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 PowerPC,P1020@0 { 58 device_type = "cpu"; 59 reg = <0x0>; 60 next-level-cache = <&L2>; 61 }; 62 63 PowerPC,P1020@1 { 64 device_type = "cpu"; 65 reg = <0x1>; 66 next-level-cache = <&L2>; 67 }; 68 }; 69 70 memory { 71 device_type = "memory"; 72 }; 73 74 localbus@ffe05000 { 75 #address-cells = <2>; 76 #size-cells = <1>; 77 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus"; 78 reg = <0 0xffe05000 0 0x1000>; 79 interrupts = <19 2>; 80 interrupt-parent = <&mpic>; 81 82 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ 83 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 84 0x1 0x0 0x0 0xffa00000 0x00040000 85 0x2 0x0 0x0 0xffb00000 0x00020000>; 86 87 nor@0,0 { 88 #address-cells = <1>; 89 #size-cells = <1>; 90 compatible = "cfi-flash"; 91 reg = <0x0 0x0 0x1000000>; 92 bank-width = <2>; 93 device-width = <1>; 94 95 partition@0 { 96 /* This location must not be altered */ 97 /* 256KB for Vitesse 7385 Switch firmware */ 98 reg = <0x0 0x00040000>; 99 label = "NOR (RO) Vitesse-7385 Firmware"; 100 read-only; 101 }; 102 103 partition@40000 { 104 /* 256KB for DTB Image */ 105 reg = <0x00040000 0x00040000>; 106 label = "NOR (RO) DTB Image"; 107 read-only; 108 }; 109 110 partition@80000 { 111 /* 3.5 MB for Linux Kernel Image */ 112 reg = <0x00080000 0x00380000>; 113 label = "NOR (RO) Linux Kernel Image"; 114 read-only; 115 }; 116 117 partition@400000 { 118 /* 11MB for JFFS2 based Root file System */ 119 reg = <0x00400000 0x00b00000>; 120 label = "NOR (RW) JFFS2 Root File System"; 121 }; 122 123 partition@f00000 { 124 /* This location must not be altered */ 125 /* 512KB for u-boot Bootloader Image */ 126 /* 512KB for u-boot Environment Variables */ 127 reg = <0x00f00000 0x00100000>; 128 label = "NOR (RO) U-Boot Image"; 129 read-only; 130 }; 131 }; 132 133 nand@1,0 { 134 #address-cells = <1>; 135 #size-cells = <1>; 136 compatible = "fsl,p1020-fcm-nand", 137 "fsl,elbc-fcm-nand"; 138 reg = <0x1 0x0 0x40000>; 139 140 partition@0 { 141 /* This location must not be altered */ 142 /* 1MB for u-boot Bootloader Image */ 143 reg = <0x0 0x00100000>; 144 label = "NAND (RO) U-Boot Image"; 145 read-only; 146 }; 147 148 partition@100000 { 149 /* 1MB for DTB Image */ 150 reg = <0x00100000 0x00100000>; 151 label = "NAND (RO) DTB Image"; 152 read-only; 153 }; 154 155 partition@200000 { 156 /* 4MB for Linux Kernel Image */ 157 reg = <0x00200000 0x00400000>; 158 label = "NAND (RO) Linux Kernel Image"; 159 read-only; 160 }; 161 162 partition@600000 { 163 /* 4MB for Compressed Root file System Image */ 164 reg = <0x00600000 0x00400000>; 165 label = "NAND (RO) Compressed RFS Image"; 166 read-only; 167 }; 168 169 partition@a00000 { 170 /* 7MB for JFFS2 based Root file System */ 171 reg = <0x00a00000 0x00700000>; 172 label = "NAND (RW) JFFS2 Root File System"; 173 }; 174 175 partition@1100000 { 176 /* 15MB for JFFS2 based Root file System */ 177 reg = <0x01100000 0x00f00000>; 178 label = "NAND (RW) Writable User area"; 179 }; 180 }; 181 182 L2switch@2,0 { 183 #address-cells = <1>; 184 #size-cells = <1>; 185 compatible = "vitesse-7385"; 186 reg = <0x2 0x0 0x20000>; 187 }; 188 189 }; 190 191 soc@ffe00000 { 192 #address-cells = <1>; 193 #size-cells = <1>; 194 device_type = "soc"; 195 compatible = "fsl,p1020-immr", "simple-bus"; 196 ranges = <0x0 0x0 0xffe00000 0x100000>; 197 bus-frequency = <0>; // Filled out by uboot. 198 199 ecm-law@0 { 200 compatible = "fsl,ecm-law"; 201 reg = <0x0 0x1000>; 202 fsl,num-laws = <12>; 203 }; 204 205 ecm@1000 { 206 compatible = "fsl,p1020-ecm", "fsl,ecm"; 207 reg = <0x1000 0x1000>; 208 interrupts = <16 2>; 209 interrupt-parent = <&mpic>; 210 }; 211 212 memory-controller@2000 { 213 compatible = "fsl,p1020-memory-controller"; 214 reg = <0x2000 0x1000>; 215 interrupt-parent = <&mpic>; 216 interrupts = <16 2>; 217 }; 218 219 i2c@3000 { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 cell-index = <0>; 223 compatible = "fsl-i2c"; 224 reg = <0x3000 0x100>; 225 interrupts = <43 2>; 226 interrupt-parent = <&mpic>; 227 dfsrr; 228 rtc@68 { 229 compatible = "dallas,ds1339"; 230 reg = <0x68>; 231 }; 232 }; 233 234 i2c@3100 { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 cell-index = <1>; 238 compatible = "fsl-i2c"; 239 reg = <0x3100 0x100>; 240 interrupts = <43 2>; 241 interrupt-parent = <&mpic>; 242 dfsrr; 243 }; 244 245 serial0: serial@4500 { 246 cell-index = <0>; 247 device_type = "serial"; 248 compatible = "ns16550"; 249 reg = <0x4500 0x100>; 250 clock-frequency = <0>; 251 interrupts = <42 2>; 252 interrupt-parent = <&mpic>; 253 }; 254 255 serial1: serial@4600 { 256 cell-index = <1>; 257 device_type = "serial"; 258 compatible = "ns16550"; 259 reg = <0x4600 0x100>; 260 clock-frequency = <0>; 261 interrupts = <42 2>; 262 interrupt-parent = <&mpic>; 263 }; 264 265 spi@7000 { 266 cell-index = <0>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 compatible = "fsl,espi"; 270 reg = <0x7000 0x1000>; 271 interrupts = <59 0x2>; 272 interrupt-parent = <&mpic>; 273 mode = "cpu"; 274 275 fsl_m25p80@0 { 276 #address-cells = <1>; 277 #size-cells = <1>; 278 compatible = "fsl,espi-flash"; 279 reg = <0>; 280 linux,modalias = "fsl_m25p80"; 281 modal = "s25sl128b"; 282 spi-max-frequency = <50000000>; 283 mode = <0>; 284 285 partition@0 { 286 /* 512KB for u-boot Bootloader Image */ 287 reg = <0x0 0x00080000>; 288 label = "SPI (RO) U-Boot Image"; 289 read-only; 290 }; 291 292 partition@80000 { 293 /* 512KB for DTB Image */ 294 reg = <0x00080000 0x00080000>; 295 label = "SPI (RO) DTB Image"; 296 read-only; 297 }; 298 299 partition@100000 { 300 /* 4MB for Linux Kernel Image */ 301 reg = <0x00100000 0x00400000>; 302 label = "SPI (RO) Linux Kernel Image"; 303 read-only; 304 }; 305 306 partition@500000 { 307 /* 4MB for Compressed RFS Image */ 308 reg = <0x00500000 0x00400000>; 309 label = "SPI (RO) Compressed RFS Image"; 310 read-only; 311 }; 312 313 partition@900000 { 314 /* 7MB for JFFS2 based RFS */ 315 reg = <0x00900000 0x00700000>; 316 label = "SPI (RW) JFFS2 RFS"; 317 }; 318 }; 319 }; 320 321 gpio: gpio-controller@f000 { 322 #gpio-cells = <2>; 323 compatible = "fsl,mpc8572-gpio"; 324 reg = <0xf000 0x100>; 325 interrupts = <47 0x2>; 326 interrupt-parent = <&mpic>; 327 gpio-controller; 328 }; 329 330 L2: l2-cache-controller@20000 { 331 compatible = "fsl,p1020-l2-cache-controller"; 332 reg = <0x20000 0x1000>; 333 cache-line-size = <32>; // 32 bytes 334 cache-size = <0x40000>; // L2,256K 335 interrupt-parent = <&mpic>; 336 interrupts = <16 2>; 337 }; 338 339 dma@21300 { 340 #address-cells = <1>; 341 #size-cells = <1>; 342 compatible = "fsl,eloplus-dma"; 343 reg = <0x21300 0x4>; 344 ranges = <0x0 0x21100 0x200>; 345 cell-index = <0>; 346 dma-channel@0 { 347 compatible = "fsl,eloplus-dma-channel"; 348 reg = <0x0 0x80>; 349 cell-index = <0>; 350 interrupt-parent = <&mpic>; 351 interrupts = <20 2>; 352 }; 353 dma-channel@80 { 354 compatible = "fsl,eloplus-dma-channel"; 355 reg = <0x80 0x80>; 356 cell-index = <1>; 357 interrupt-parent = <&mpic>; 358 interrupts = <21 2>; 359 }; 360 dma-channel@100 { 361 compatible = "fsl,eloplus-dma-channel"; 362 reg = <0x100 0x80>; 363 cell-index = <2>; 364 interrupt-parent = <&mpic>; 365 interrupts = <22 2>; 366 }; 367 dma-channel@180 { 368 compatible = "fsl,eloplus-dma-channel"; 369 reg = <0x180 0x80>; 370 cell-index = <3>; 371 interrupt-parent = <&mpic>; 372 interrupts = <23 2>; 373 }; 374 }; 375 376 mdio@24000 { 377 #address-cells = <1>; 378 #size-cells = <0>; 379 compatible = "fsl,etsec2-mdio"; 380 reg = <0x24000 0x1000 0xb0030 0x4>; 381 382 phy0: ethernet-phy@0 { 383 interrupt-parent = <&mpic>; 384 interrupts = <3 1>; 385 reg = <0x0>; 386 }; 387 388 phy1: ethernet-phy@1 { 389 interrupt-parent = <&mpic>; 390 interrupts = <2 1>; 391 reg = <0x1>; 392 }; 393 }; 394 395 mdio@25000 { 396 #address-cells = <1>; 397 #size-cells = <0>; 398 compatible = "fsl,etsec2-tbi"; 399 reg = <0x25000 0x1000 0xb1030 0x4>; 400 401 tbi0: tbi-phy@11 { 402 reg = <0x11>; 403 device_type = "tbi-phy"; 404 }; 405 }; 406 407 enet0: ethernet@b0000 { 408 #address-cells = <1>; 409 #size-cells = <1>; 410 device_type = "network"; 411 model = "eTSEC"; 412 compatible = "fsl,etsec2"; 413 fsl,num_rx_queues = <0x8>; 414 fsl,num_tx_queues = <0x8>; 415 local-mac-address = [ 00 00 00 00 00 00 ]; 416 interrupt-parent = <&mpic>; 417 fixed-link = <1 1 1000 0 0>; 418 phy-connection-type = "rgmii-id"; 419 420 queue-group@0 { 421 #address-cells = <1>; 422 #size-cells = <1>; 423 reg = <0xb0000 0x1000>; 424 interrupts = <29 2 30 2 34 2>; 425 }; 426 427 queue-group@1 { 428 #address-cells = <1>; 429 #size-cells = <1>; 430 reg = <0xb4000 0x1000>; 431 interrupts = <17 2 18 2 24 2>; 432 }; 433 }; 434 435 enet1: ethernet@b1000 { 436 #address-cells = <1>; 437 #size-cells = <1>; 438 device_type = "network"; 439 model = "eTSEC"; 440 compatible = "fsl,etsec2"; 441 fsl,num_rx_queues = <0x8>; 442 fsl,num_tx_queues = <0x8>; 443 local-mac-address = [ 00 00 00 00 00 00 ]; 444 interrupt-parent = <&mpic>; 445 phy-handle = <&phy0>; 446 tbi-handle = <&tbi0>; 447 phy-connection-type = "sgmii"; 448 449 queue-group@0 { 450 #address-cells = <1>; 451 #size-cells = <1>; 452 reg = <0xb1000 0x1000>; 453 interrupts = <35 2 36 2 40 2>; 454 }; 455 456 queue-group@1 { 457 #address-cells = <1>; 458 #size-cells = <1>; 459 reg = <0xb5000 0x1000>; 460 interrupts = <51 2 52 2 67 2>; 461 }; 462 }; 463 464 enet2: ethernet@b2000 { 465 #address-cells = <1>; 466 #size-cells = <1>; 467 device_type = "network"; 468 model = "eTSEC"; 469 compatible = "fsl,etsec2"; 470 fsl,num_rx_queues = <0x8>; 471 fsl,num_tx_queues = <0x8>; 472 local-mac-address = [ 00 00 00 00 00 00 ]; 473 interrupt-parent = <&mpic>; 474 phy-handle = <&phy1>; 475 phy-connection-type = "rgmii-id"; 476 477 queue-group@0 { 478 #address-cells = <1>; 479 #size-cells = <1>; 480 reg = <0xb2000 0x1000>; 481 interrupts = <31 2 32 2 33 2>; 482 }; 483 484 queue-group@1 { 485 #address-cells = <1>; 486 #size-cells = <1>; 487 reg = <0xb6000 0x1000>; 488 interrupts = <25 2 26 2 27 2>; 489 }; 490 }; 491 492 usb@22000 { 493 #address-cells = <1>; 494 #size-cells = <0>; 495 compatible = "fsl-usb2-dr"; 496 reg = <0x22000 0x1000>; 497 interrupt-parent = <&mpic>; 498 interrupts = <28 0x2>; 499 phy_type = "ulpi"; 500 }; 501 502 /* USB2 is shared with localbus, so it must be disabled 503 by default. We can't put 'status = "disabled";' here 504 since U-Boot doesn't clear the status property when 505 it enables USB2. OTOH, U-Boot does create a new node 506 when there isn't any. So, just comment it out. 507 usb@23000 { 508 #address-cells = <1>; 509 #size-cells = <0>; 510 compatible = "fsl-usb2-dr"; 511 reg = <0x23000 0x1000>; 512 interrupt-parent = <&mpic>; 513 interrupts = <46 0x2>; 514 phy_type = "ulpi"; 515 }; 516 */ 517 518 sdhci@2e000 { 519 compatible = "fsl,p1020-esdhc", "fsl,esdhc"; 520 reg = <0x2e000 0x1000>; 521 interrupts = <72 0x2>; 522 interrupt-parent = <&mpic>; 523 /* Filled in by U-Boot */ 524 clock-frequency = <0>; 525 }; 526 527 crypto@30000 { 528 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", 529 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; 530 reg = <0x30000 0x10000>; 531 interrupts = <45 2 58 2>; 532 interrupt-parent = <&mpic>; 533 fsl,num-channels = <4>; 534 fsl,channel-fifo-len = <24>; 535 fsl,exec-units-mask = <0xbfe>; 536 fsl,descriptor-types-mask = <0x3ab0ebf>; 537 }; 538 539 mpic: pic@40000 { 540 interrupt-controller; 541 #address-cells = <0>; 542 #interrupt-cells = <2>; 543 reg = <0x40000 0x40000>; 544 compatible = "chrp,open-pic"; 545 device_type = "open-pic"; 546 }; 547 548 msi@41600 { 549 compatible = "fsl,p1020-msi", "fsl,mpic-msi"; 550 reg = <0x41600 0x80>; 551 msi-available-ranges = <0 0x100>; 552 interrupts = < 553 0xe0 0 554 0xe1 0 555 0xe2 0 556 0xe3 0 557 0xe4 0 558 0xe5 0 559 0xe6 0 560 0xe7 0>; 561 interrupt-parent = <&mpic>; 562 }; 563 564 global-utilities@e0000 { //global utilities block 565 compatible = "fsl,p1020-guts"; 566 reg = <0xe0000 0x1000>; 567 fsl,has-rstcr; 568 }; 569 }; 570 571 pci0: pcie@ffe09000 { 572 compatible = "fsl,mpc8548-pcie"; 573 device_type = "pci"; 574 #interrupt-cells = <1>; 575 #size-cells = <2>; 576 #address-cells = <3>; 577 reg = <0 0xffe09000 0 0x1000>; 578 bus-range = <0 255>; 579 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 580 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 581 clock-frequency = <33333333>; 582 interrupt-parent = <&mpic>; 583 interrupts = <16 2>; 584 pcie@0 { 585 reg = <0x0 0x0 0x0 0x0 0x0>; 586 #size-cells = <2>; 587 #address-cells = <3>; 588 device_type = "pci"; 589 ranges = <0x2000000 0x0 0xa0000000 590 0x2000000 0x0 0xa0000000 591 0x0 0x20000000 592 593 0x1000000 0x0 0x0 594 0x1000000 0x0 0x0 595 0x0 0x100000>; 596 }; 597 }; 598 599 pci1: pcie@ffe0a000 { 600 compatible = "fsl,mpc8548-pcie"; 601 device_type = "pci"; 602 #interrupt-cells = <1>; 603 #size-cells = <2>; 604 #address-cells = <3>; 605 reg = <0 0xffe0a000 0 0x1000>; 606 bus-range = <0 255>; 607 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 608 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 609 clock-frequency = <33333333>; 610 interrupt-parent = <&mpic>; 611 interrupts = <16 2>; 612 pcie@0 { 613 reg = <0x0 0x0 0x0 0x0 0x0>; 614 #size-cells = <2>; 615 #address-cells = <3>; 616 device_type = "pci"; 617 ranges = <0x2000000 0x0 0xc0000000 618 0x2000000 0x0 0xc0000000 619 0x0 0x20000000 620 621 0x1000000 0x0 0x0 622 0x1000000 0x0 0x0 623 0x0 0x100000>; 624 }; 625 }; 626}; 627