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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode() argument
89 if (RC == &WebAssembly::I32RegClass) in getDropOpcode()
91 if (RC == &WebAssembly::I64RegClass) in getDropOpcode()
93 if (RC == &WebAssembly::F32RegClass) in getDropOpcode()
95 if (RC == &WebAssembly::F64RegClass) in getDropOpcode()
97 if (RC == &WebAssembly::V128RegClass) in getDropOpcode()
99 if (RC == &WebAssembly::FUNCREFRegClass) in getDropOpcode()
101 if (RC == &WebAssembly::EXTERNREFRegClass) in getDropOpcode()
103 if (RC == &WebAssembly::EXNREFRegClass) in getDropOpcode()
109 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
93 unsigned ID = RC.getID(); in mask()
96 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); in mask()
108 << TRI.getRegClassName(&RC) << '\n'; in mask()
117 for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass, in getPhysRegBitWidth()
119 if (RC.contains(Reg)) in getPhysRegBitWidth()
120 return TRI.getRegSizeInBits(RC); in getPhysRegBitWidth()
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
124 return TRI.getRegSizeInBits(*RC); in getPhysRegBitWidth()
131 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
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H A DBitTracker.h54 void put(RegisterRef RR, const RegisterCell &RC);
316 bool meet(const RegisterCell &RC, Register SelfR);
317 RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
321 RegisterCell &cat(const RegisterCell &RC); // Concatenate.
325 bool operator== (const RegisterCell &RC) const;
326 bool operator!= (const RegisterCell &RC) const {
327 return !operator==(RC);
349 friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
365 RegisterCell RC(Width); in self()
367 RC.Bits[i] = BitValue::self(BitRef(Reg, i)); in self()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h76 /// class \p RC.
79 const TargetRegisterClass *RC) const;
107 getLargestLegalSuperClass(const TargetRegisterClass *RC,
144 /// a cross register class copy, return the specified RC. Returns NULL if it
147 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
198 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClassID()
199 return hasSGPRs(RC) && !hasVGPRs(RC) && !hasAGPRs(RC); in isSGPRClassID()
210 static bool isVGPRClass(const TargetRegisterClass *RC) { in isAGPRClass()
192 isSGPRClass(const TargetRegisterClass * RC) isSGPRClass() argument
204 isVGPRClass(const TargetRegisterClass * RC) isVGPRClass() argument
209 isAGPRClass(const TargetRegisterClass * RC) isAGPRClass() argument
214 isVectorSuperClass(const TargetRegisterClass * RC) isVectorSuperClass() argument
219 isVSSuperClass(const TargetRegisterClass * RC) isVSSuperClass() argument
224 hasVGPRs(const TargetRegisterClass * RC) hasVGPRs() argument
229 hasAGPRs(const TargetRegisterClass * RC) hasAGPRs() argument
234 hasSGPRs(const TargetRegisterClass * RC) hasSGPRs() argument
239 hasVectorRegisters(const TargetRegisterClass * RC) hasVectorRegisters() argument
299 isDivergentRegClass(const TargetRegisterClass * RC) isDivergentRegClass() argument
429 getRegClassAlignmentNumBits(const TargetRegisterClass * RC) getRegClassAlignmentNumBits() argument
434 isRegClassAligned(const TargetRegisterClass * RC,unsigned AlignNumBits) isRegClassAligned() argument
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H A DGCNRewritePartialRegUses.cpp81 const TargetRegisterClass *RC; member
87 SubRegInfo(const TargetRegisterClass *RC_ = nullptr) : RC(RC_) {} in SubRegInfo()
97 const TargetRegisterClass *getMinSizeReg(const TargetRegisterClass *RC,
116 getRegClassWithShiftedSubregs(const TargetRegisterClass *RC, unsigned RShift,
143 const uint32_t *getSuperRegClassMask(const TargetRegisterClass *RC,
187 GCNRewritePartialRegUses::getSuperRegClassMask(const TargetRegisterClass *RC, in getSuperRegClassMask() argument
190 SuperRegMasks.try_emplace({RC, SubRegIdx}, nullptr); in getSuperRegClassMask()
192 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) { in getSuperRegClassMask()
210 auto *RC = TRI->getRegClass(ClassID); in getAllocatableAndAlignedRegClassMask() local
211 if (RC->isAllocatable() && TRI->isRegClassAligned(RC, AlignNumBits)) in getAllocatableAndAlignedRegClassMask()
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/freebsd/contrib/ofed/libibverbs/
H A Dopcode.h83 IBV_OPCODE(RC, SEND_FIRST),
84 IBV_OPCODE(RC, SEND_MIDDLE),
85 IBV_OPCODE(RC, SEND_LAST),
86 IBV_OPCODE(RC, SEND_LAST_WITH_IMMEDIATE),
87 IBV_OPCODE(RC, SEND_ONLY),
88 IBV_OPCODE(RC, SEND_ONLY_WITH_IMMEDIATE),
89 IBV_OPCODE(RC, RDMA_WRITE_FIRST),
90 IBV_OPCODE(RC, RDMA_WRITE_MIDDLE),
91 IBV_OPCODE(RC, RDMA_WRITE_LAST),
92 IBV_OPCODE(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE),
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA.td36 multiclass fma3p_rm_213<bits<8> opc, string OpcodeStr, RegisterClass RC,
39 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
40 (ins RC:$src1, RC:$src2, RC:$src3),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
47 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
56 multiclass fma3p_rm_231<bits<8> opc, string OpcodeStr, RegisterClass RC,
60 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
61 (ins RC:$src1, RC:$src2, RC:$src3),
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H A DX86InstrAVX512.td78 [(set _.RC:$dst, RHS)],
79 [(set _.RC:$dst, MaskingRHS)],
80 [(set _.RC:$dst,
97 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
100 [(set _.RC:$dst, RHS)],
101 [(set _.RC:$dst,
102 (vselect_mask _.KRCWM:$mask, MaskRHS, _.RC:$src0))],
103 [(set _.RC:$dst,
120 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
123 (Select _.KRCWM:$mask, RHS, _.RC:$src0),
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName() argument
30 if (RC == &NVPTX::Float32RegsRegClass) in getNVPTXRegClassName()
32 if (RC == &NVPTX::Float64RegsRegClass) in getNVPTXRegClassName()
34 if (RC == &NVPTX::Int128RegsRegClass) in getNVPTXRegClassName()
36 if (RC == &NVPTX::Int64RegsRegClass) in getNVPTXRegClassName()
56 if (RC == &NVPTX::Int32RegsRegClass) in getNVPTXRegClassName()
58 if (RC == &NVPTX::Int16RegsRegClass) in getNVPTXRegClassName()
60 if (RC == &NVPTX::Int1RegsRegClass) in getNVPTXRegClassName()
62 if (RC == &NVPTX::SpecialRegsRegClass) in getNVPTXRegClassName()
67 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr() argument
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/freebsd/sys/ofed/include/rdma/
H A Dib_pack.h115 IB_OPCODE(RC, SEND_FIRST),
116 IB_OPCODE(RC, SEND_MIDDLE),
117 IB_OPCODE(RC, SEND_LAST),
118 IB_OPCODE(RC, SEND_LAST_WITH_IMMEDIATE),
119 IB_OPCODE(RC, SEND_ONLY),
120 IB_OPCODE(RC, SEND_ONLY_WITH_IMMEDIATE),
121 IB_OPCODE(RC, RDMA_WRITE_FIRST),
122 IB_OPCODE(RC, RDMA_WRITE_MIDDLE),
123 IB_OPCODE(RC, RDMA_WRITE_LAST),
124 IB_OPCODE(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE),
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h75 void compute(const TargetRegisterClass *RC) const;
78 const RCInfo &get(const TargetRegisterClass *RC) const { in get() argument
79 const RCInfo &RCI = RegClass[RC->getID()]; in get()
81 compute(RC); in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() argument
95 return get(RC).NumRegs; in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() argument
102 return get(RC); in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass() argument
112 return get(RC).ProperSubClass; in isProperSubClass()
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H A DTargetRegisterInfo.h126 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass() argument
127 return RC != this && hasSubClassEq(RC); in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() argument
132 unsigned ID = RC->getID(); in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass() argument
139 return RC->hasSubClass(this); in hasSuperClass()
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() argument
144 return RC->hasSubClassEq(this); in hasSuperClassEq()
297 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits() argument
298 return TypeSize::getFixed(getRegClassInfo(RC).RegSize); in getRegSizeInBits()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp74 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass() argument
75 if (llvm::is_contained(RCs, RC)) in addRegisterClass()
87 RCsWithLargestRegSize[M] = RC; in addRegisterClass()
89 RC->RSI.get(M).SpillSize) in addRegisterClass()
90 RCsWithLargestRegSize[M] = RC; in addRegisterClass()
94 RCs.emplace_back(RC); in addRegisterClass()
176 const CodeGenRegisterClass *RC, const Twine &Kind, in visitRegisterBankClasses() argument
181 if (!VisitedRCs.insert(RC).second) in visitRegisterBankClasses()
185 VisitFn(RC, Kind.str()); in visitRegisterBankClasses()
192 if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass)) in visitRegisterBankClasses()
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H A DRegisterInfoEmitter.cpp148 for (const auto &RC : RegisterClasses) in runEnums() local
149 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; in runEnums()
217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure()
219 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
220 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure()
227 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
1008 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1009 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h120 getLargestLegalSuperClass(const TargetRegisterClass *RC,
134 getLargestSuperClass(const TargetRegisterClass *RC) const override { in getLargestSuperClass()
135 if (RISCV::VRM8RegClass.hasSubClassEq(RC)) in getLargestSuperClass()
137 if (RISCV::VRM4RegClass.hasSubClassEq(RC)) in getLargestSuperClass()
139 if (RISCV::VRM2RegClass.hasSubClassEq(RC)) in getLargestSuperClass()
141 if (RISCV::VRRegClass.hasSubClassEq(RC)) in getLargestSuperClass()
143 return RC; in getLargestSuperClass()
147 const TargetRegisterClass *RC) const override { in doesRegClassHavePseudoInitUndef()
148 return isVRRegClass(RC); in doesRegClassHavePseudoInitUndef()
151 static bool isVRRegClass(const TargetRegisterClass *RC) { in isVRRegClass()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp192 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
193 if (!RC || RC->isAllocatable()) in getAllocatableClass()
194 return RC; in getAllocatableClass()
196 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid(); in getAllocatableClass()
216 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass() local
217 if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) && in getMinimalPhysRegClass()
218 RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC))) in getMinimalPhysRegClass()
219 BestRC = RC; in getMinimalPhysRegClass()
234 for (const TargetRegisterClass *RC : regclasses()) { in getMinimalPhysRegClassLLT() local
235 if ((!Ty.isValid() || isTypeLegalForClass(*RC, Ty)) && RC->contains(reg) && in getMinimalPhysRegClassLLT()
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H A DRegisterClassInfo.cpp125 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { in compute()
126 assert(RC && "no register class given"); in compute()
127 RCInfo &RCI = RegClass[RC->getID()]; in compute()
131 unsigned NumRegs = RC->getNumRegs(); in compute()
144 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); in compute()
181 TRI->getLargestLegalSuperClass(RC, *MF)) in compute()
182 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
189 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
203 const TargetRegisterClass *RC = nullptr; in computePSetLimit() local
217 if (!RC || NUnits > NumRCUnits) { in computePSetLimit()
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H A DRegisterBank.cpp26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in RegisterBank()
28 if (!covers(RC)) in RegisterBank()
34 // RegisterBankInfo to find the subclasses of RC, to make sure in verify()
39 if (!RC.hasSubClassEq(&SubRC)) in verify()
52 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in verify()
53 return (CoveredClasses[RC.getID() / 32] & (1U << RC.getID() % 32)) != 0; in verify()
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
94 if (covers(RC)) in print()
95 OS << LS << TRI->getRegClassName(&RC); in print()
37 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); verify() local
107 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); print() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCondMov.td35 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
45 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
267 class Select_Pseudo<RegisterOperand RC> :
268 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
269 [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
272 class SelectFP_Pseudo_T<RegisterOperand RC> :
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H A DMipsInstrFPU.td111 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
113 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
185 class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
187 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
188 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,
194 class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
196 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
197 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {
202 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
50 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
52 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
53 TRI.getSpillAlign(RC), true); in createLRSpillSlot()
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
67 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
79 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
80 Align Alignment = TRI.getSpillAlign(RC); in createEHSpillSlot()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstantFolder.h46 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
47 if (LC && RC) { in FoldBinOp()
49 return ConstantExpr::get(Opc, LC, RC); in FoldBinOp()
50 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldBinOp()
58 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
59 if (LC && RC) { in FoldExactBinOp()
61 return ConstantExpr::get(Opc, LC, RC, in FoldExactBinOp()
63 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldExactBinOp()
71 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
72 if (LC && RC) { in FoldNoWrapBinOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td129 multiclass VLDbm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in,
132 def "" : RVM<opc, (outs RC:$vx), dag_in,
136 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
139 multiclass VLDlm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> {
140 defm "" : VLDbm<opcStr, opc, RC, dag_in>;
142 defm l : VLDbm<opcStr, opc, RC, !con(dag_in, (ins I32:$vl)), "$vl,">;
143 defm L : VLDbm<opcStr, opc, RC, !con(dag_in, (ins VLS:$vl)), "$vl,">;
147 multiclass VLDtgm<string opcStr, bits<8>opc, RegisterClass RC> {
148 defm rr : VLDlm<opcStr, opc, RC, (ins I64:$sy, I64:$sz)>;
150 defm ir : VLDlm<opcStr, opc, RC, (ins simm7:$sy, I64:$sz)>;
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1011 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
1012 RC.SubClasses.resize(RegClasses.size()); in computeSubClasses()
1013 RC.SubClasses.set(RC.EnumValue); in computeSubClasses()
1014 if (RC.Artificial) in computeSubClasses()
1020 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
1022 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
1026 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
1030 for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2) in computeSubClasses()
1031 RC.SubClasses.set(I2->EnumValue); in computeSubClasses()
1035 for (auto &RC : RegClasses) { in computeSubClasses() local
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetFolder.h57 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
58 if (LC && RC) { in FoldBinOp()
60 return Fold(ConstantExpr::get(Opc, LC, RC)); in FoldBinOp()
61 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldBinOp()
69 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
70 if (LC && RC) { in FoldExactBinOp()
73 Opc, LC, RC, IsExact ? PossiblyExactOperator::IsExact : 0)); in FoldExactBinOp()
74 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldExactBinOp()
82 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
83 if (LC && RC) { in FoldNoWrapBinOp()
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