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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode() argument
89 if (RC == &WebAssembly::I32RegClass) in getDropOpcode()
91 if (RC == &WebAssembly::I64RegClass) in getDropOpcode()
93 if (RC == &WebAssembly::F32RegClass) in getDropOpcode()
95 if (RC == &WebAssembly::F64RegClass) in getDropOpcode()
97 if (RC == &WebAssembly::V128RegClass) in getDropOpcode()
99 if (RC == &WebAssembly::FUNCREFRegClass) in getDropOpcode()
101 if (RC == &WebAssembly::EXTERNREFRegClass) in getDropOpcode()
103 if (RC == &WebAssembly::EXNREFRegClass) in getDropOpcode()
109 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp82 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
83 unsigned ID = RC.getID(); in mask()
86 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); in mask()
99 << TRI.getRegClassName(&RC) << '\n'; in mask()
108 for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass, in getPhysRegBitWidth()
110 if (RC.contains(Reg)) in getPhysRegBitWidth()
111 return TRI.getRegSizeInBits(RC); in getPhysRegBitWidth()
114 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
115 return TRI.getRegSizeInBits(*RC); in getPhysRegBitWidth()
122 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
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H A DBitTracker.h51 void put(RegisterRef RR, const RegisterCell &RC);
313 bool meet(const RegisterCell &RC, Register SelfR);
314 RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
318 RegisterCell &cat(const RegisterCell &RC); // Concatenate.
322 bool operator== (const RegisterCell &RC) const;
323 bool operator!= (const RegisterCell &RC) const {
324 return !operator==(RC);
346 friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
362 RegisterCell RC(Width); in self()
364 RC.Bits[i] = BitValue::self(BitRef(Reg, i)); in self()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h87 const TargetRegisterClass *RC) const;
130 getLargestLegalSuperClass(const TargetRegisterClass *RC,
170 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
226 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClass() argument
227 return hasSGPRs(RC) && !hasVGPRs(RC) && !hasAGPRs(RC); in isSGPRClass()
245 static bool isVGPRClass(const TargetRegisterClass *RC) { in isVGPRClass() argument
246 return hasVGPRs(RC) && !hasAGPRs(RC) && !hasSGPRs(RC); in isVGPRClass()
250 static bool isAGPRClass(const TargetRegisterClass *RC) { in isAGPRClass() argument
251 return hasAGPRs(RC) && !hasVGPRs(RC) && !hasSGPRs(RC); in isAGPRClass()
255 bool isVectorSuperClass(const TargetRegisterClass *RC) const { in isVectorSuperClass() argument
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H A DGCNRewritePartialRegUses.cpp66 const TargetRegisterClass *getMinSizeReg(const TargetRegisterClass *RC,
83 getRegClassWithShiftedSubregs(const TargetRegisterClass *RC, unsigned RShift,
107 const uint32_t *getSuperRegClassMask(const TargetRegisterClass *RC,
174 const TargetRegisterClass *RC, unsigned SubRegIdx) const { in getSuperRegClassMask() argument
176 SuperRegMasks.try_emplace({RC, SubRegIdx}, nullptr); in getSuperRegClassMask()
178 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) { in getSuperRegClassMask()
197 auto *RC = TRI->getRegClass(ClassID); in getAllocatableAndAlignedRegClassMask() local
198 if (RC->isAllocatable() && TRI->isRegClassAligned(RC, AlignNumBits)) in getAllocatableAndAlignedRegClassMask()
207 const TargetRegisterClass *RC, unsigned RShift, unsigned CoverSubregIdx, in getRegClassWithShiftedSubregs() argument
210 unsigned RCAlign = TRI->getRegClassAlignmentNumBits(RC); in getRegClassWithShiftedSubregs()
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/freebsd/contrib/ofed/libibverbs/
H A Dopcode.h83 IBV_OPCODE(RC, SEND_FIRST),
84 IBV_OPCODE(RC, SEND_MIDDLE),
85 IBV_OPCODE(RC, SEND_LAST),
86 IBV_OPCODE(RC, SEND_LAST_WITH_IMMEDIATE),
87 IBV_OPCODE(RC, SEND_ONLY),
88 IBV_OPCODE(RC, SEND_ONLY_WITH_IMMEDIATE),
89 IBV_OPCODE(RC, RDMA_WRITE_FIRST),
90 IBV_OPCODE(RC, RDMA_WRITE_MIDDLE),
91 IBV_OPCODE(RC, RDMA_WRITE_LAST),
92 IBV_OPCODE(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE),
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA.td36 multiclass fma3p_rm_213<bits<8> opc, string OpcodeStr, RegisterClass RC,
39 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
40 (ins RC:$src1, RC:$src2, RC:$src3),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
47 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
56 multiclass fma3p_rm_231<bits<8> opc, string OpcodeStr, RegisterClass RC,
60 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
61 (ins RC:$src1, RC:$src2, RC:$src3),
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H A DX86InstrAVX512.td80 [(set _.RC:$dst, RHS)],
81 [(set _.RC:$dst, MaskingRHS)],
82 [(set _.RC:$dst,
100 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
103 [(set _.RC:$dst, RHS)],
104 [(set _.RC:$dst,
105 (vselect_mask _.KRCWM:$mask, MaskRHS, _.RC:$src0))],
106 [(set _.RC:$dst,
124 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
127 (Select _.KRCWM:$mask, RHS, _.RC:$src0),
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp76 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass() argument
77 if (llvm::is_contained(RCs, RC)) in addRegisterClass()
89 RCsWithLargestRegSize[M] = RC; in addRegisterClass()
91 RC->RSI.get(M).SpillSize) in addRegisterClass()
92 RCsWithLargestRegSize[M] = RC; in addRegisterClass()
96 RCs.emplace_back(RC); in addRegisterClass()
180 const CodeGenRegisterClass *RC, const Twine &Kind, in visitRegisterBankClasses() argument
185 if (!VisitedRCs.insert(RC).second) in visitRegisterBankClasses()
189 VisitFn(RC, Kind.str()); in visitRegisterBankClasses()
196 if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass)) in visitRegisterBankClasses()
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H A DRegisterInfoEmitter.cpp144 for (const auto &RC : RegisterClasses) in runEnums() local
145 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; in runEnums()
211 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
212 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure()
213 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
214 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
218 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure()
221 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
1045 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1046 ArrayRef<const Record *> Order = RC.getOrder(); in runMCDesc()
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/freebsd/sys/ofed/include/rdma/
H A Dib_pack.h115 IB_OPCODE(RC, SEND_FIRST),
116 IB_OPCODE(RC, SEND_MIDDLE),
117 IB_OPCODE(RC, SEND_LAST),
118 IB_OPCODE(RC, SEND_LAST_WITH_IMMEDIATE),
119 IB_OPCODE(RC, SEND_ONLY),
120 IB_OPCODE(RC, SEND_ONLY_WITH_IMMEDIATE),
121 IB_OPCODE(RC, RDMA_WRITE_FIRST),
122 IB_OPCODE(RC, RDMA_WRITE_MIDDLE),
123 IB_OPCODE(RC, RDMA_WRITE_LAST),
124 IB_OPCODE(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE),
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h78 LLVM_ABI void compute(const TargetRegisterClass *RC) const;
81 const RCInfo &get(const TargetRegisterClass *RC) const { in get() argument
82 const RCInfo &RCI = RegClass[RC->getID()]; in get()
84 compute(RC); in get()
99 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs() argument
100 return get(RC).NumRegs; in getNumAllocatableRegs()
106 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() argument
107 return get(RC); in getOrder()
116 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass() argument
117 return get(RC).ProperSubClass; in isProperSubClass()
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H A DTargetRegisterInfo.h126 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass() argument
127 return RC != this && hasSubClassEq(RC); in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() argument
132 unsigned ID = RC->getID(); in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass() argument
139 return RC->hasSubClass(this); in hasSuperClass()
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() argument
144 return RC->hasSubClassEq(this); in hasSuperClassEq()
296 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits() argument
297 return TypeSize::getFixed(getRegClassInfo(RC).RegSize); in getRegSizeInBits()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp27 StringRef getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName() argument
28 if (RC == &NVPTX::B128RegClass) in getNVPTXRegClassName()
30 if (RC == &NVPTX::B64RegClass) in getNVPTXRegClassName()
50 if (RC == &NVPTX::B32RegClass) in getNVPTXRegClassName()
52 if (RC == &NVPTX::B16RegClass) in getNVPTXRegClassName()
54 if (RC == &NVPTX::B1RegClass) in getNVPTXRegClassName()
56 if (RC == &NVPTX::SpecialRegsRegClass) in getNVPTXRegClassName()
61 StringRef getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr() argument
62 if (RC == &NVPTX::B128RegClass) in getNVPTXRegClassStr()
64 if (RC == &NVPTX::B64RegClass) in getNVPTXRegClassStr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCondMov.td35 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
45 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
267 class Select_Pseudo<RegisterOperand RC> :
268 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
269 [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
272 class SelectFP_Pseudo_T<RegisterOperand RC> :
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H A DMipsInstrFPU.td111 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
113 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
185 class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
187 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
188 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,
194 class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
196 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
197 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {
202 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp128 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { in compute()
129 assert(RC && "no register class given"); in compute()
130 RCInfo &RCI = RegClass[RC->getID()]; in compute()
134 unsigned NumRegs = RC->getNumRegs(); in compute()
147 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF, Reverse); in compute()
189 TRI->getLargestLegalSuperClass(RC, *MF)) in compute()
190 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
197 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
211 const TargetRegisterClass *RC = nullptr; in computePSetLimit() local
225 if (!RC || NUnits > NumRCUnits) { in computePSetLimit()
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H A DTargetRegisterInfo.cpp191 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
192 if (!RC || RC->isAllocatable()) in getAllocatableClass()
193 return RC; in getAllocatableClass()
195 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid(); in getAllocatableClass()
221 for (const TargetRegisterClass *RC : TRI->regclasses()) { in getMinimalPhysRegClass() local
222 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) && RC->contains(Reg) && in getMinimalPhysRegClass()
223 (!BestRC || BestRC->hasSubClass(RC))) in getMinimalPhysRegClass()
224 BestRC = RC; in getMinimalPhysRegClass()
250 for (const TargetRegisterClass *RC : TRI->regclasses()) { in getCommonMinimalPhysRegClass() local
251 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) && in getCommonMinimalPhysRegClass()
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H A DRegisterBank.cpp26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in RegisterBank()
28 if (!covers(RC)) in RegisterBank()
34 // RegisterBankInfo to find the subclasses of RC, to make sure in verify()
39 if (!RC.hasSubClassEq(&SubRC)) in verify()
52 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in verify()
53 return (CoveredClasses[RC.getID() / 32] & (1U << RC.getID() % 32)) != 0; in verify()
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
94 if (covers(RC)) in print()
95 OS << LS << TRI->getRegClassName(&RC); in print()
37 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); verify() local
107 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); print() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
50 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
52 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
53 TRI.getSpillAlign(RC), true); in createLRSpillSlot()
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
67 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
79 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
80 Align Alignment = TRI.getSpillAlign(RC); in createEHSpillSlot()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstantFolder.h47 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
48 if (LC && RC) { in FoldBinOp()
50 return ConstantExpr::get(Opc, LC, RC); in FoldBinOp()
51 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldBinOp()
59 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
60 if (LC && RC) { in FoldExactBinOp()
62 return ConstantExpr::get(Opc, LC, RC, in FoldExactBinOp()
64 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldExactBinOp()
72 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
73 if (LC && RC) { in FoldNoWrapBinOp()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp935 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
936 RC.SubClasses.resize(NumRegClasses); in computeSubClasses()
937 RC.SubClasses.set(RC.EnumValue); in computeSubClasses()
938 if (RC.Artificial) in computeSubClasses()
944 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
946 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
950 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
954 for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2) in computeSubClasses()
955 RC.SubClasses.set(I2->EnumValue); in computeSubClasses()
959 for (auto &RC : RegClasses) { in computeSubClasses() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td129 multiclass VLDbm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in,
132 def "" : RVM<opc, (outs RC:$vx), dag_in,
136 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
139 multiclass VLDlm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> {
140 defm "" : VLDbm<opcStr, opc, RC, dag_in>;
142 defm l : VLDbm<opcStr, opc, RC, !con(dag_in, (ins I32:$vl)), "$vl,">;
143 defm L : VLDbm<opcStr, opc, RC, !con(dag_in, (ins VLS:$vl)), "$vl,">;
147 multiclass VLDtgm<string opcStr, bits<8>opc, RegisterClass RC> {
148 defm rr : VLDlm<opcStr, opc, RC, (ins I64:$sy, I64:$sz)>;
150 defm ir : VLDlm<opcStr, opc, RC, (ins simm7:$sy, I64:$sz)>;
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetFolder.h58 auto *RC = dyn_cast<Constant>(RHS); in FoldBinOp() local
59 if (LC && RC) { in FoldBinOp()
61 return Fold(ConstantExpr::get(Opc, LC, RC)); in FoldBinOp()
62 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldBinOp()
70 auto *RC = dyn_cast<Constant>(RHS); in FoldExactBinOp() local
71 if (LC && RC) { in FoldExactBinOp()
74 Opc, LC, RC, IsExact ? PossiblyExactOperator::IsExact : 0)); in FoldExactBinOp()
75 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldExactBinOp()
83 auto *RC = dyn_cast<Constant>(RHS); in FoldNoWrapBinOp() local
84 if (LC && RC) { in FoldNoWrapBinOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h132 getLargestLegalSuperClass(const TargetRegisterClass *RC,
140 float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const override;
147 static bool isVRRegClass(const TargetRegisterClass *RC) { in isVRRegClass()
148 return RISCVRI::isVRegClass(RC->TSFlags) && in isVRRegClass()
149 RISCVRI::getNF(RC->TSFlags) == 1; in isVRRegClass()
152 static bool isVRNRegClass(const TargetRegisterClass *RC) { in isVRNRegClass()
153 return RISCVRI::isVRegClass(RC->TSFlags) && RISCVRI::getNF(RC->TSFlags) > 1; in isVRNRegClass()
156 static bool isRVVRegClass(const TargetRegisterClass *RC) { in isRVVRegClass()
157 return RISCVRI::isVRegClass(RC->TSFlags); in isRVVRegClass()

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