Lines Matching refs:RC
148 for (const auto &RC : RegisterClasses) in runEnums() local
149 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; in runEnums()
217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure()
219 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
220 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure()
227 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
1008 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1009 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc()
1012 const std::string &Name = RC.getName(); in runMCDesc()
1044 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1045 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc()
1046 std::string RCName = Order.empty() ? "nullptr" : RC.getName(); in runMCDesc()
1047 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits"; in runMCDesc()
1049 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); in runMCDesc()
1051 if (RC.RSI.isSimple()) in runMCDesc()
1052 RegSize = RC.RSI.getSimple().RegSize; in runMCDesc()
1054 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1055 << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", " in runMCDesc()
1056 << RegSize << ", " << RC.CopyCost << ", " in runMCDesc()
1057 << (RC.Allocatable ? "true" : "false") << ", " in runMCDesc()
1058 << (RC.getBaseClassOrder() ? "true" : "false") << " },\n"; in runMCDesc()
1163 [](const auto &RC) { return RC.getBaseClassOrder(); })) { in runTargetHeader() argument
1174 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1175 const std::string &Name = RC.getName(); in runTargetHeader()
1210 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1211 ArrayRef<Record *> Order = RC.getOrder(); in runTargetDesc()
1213 if (RC.Allocatable) in runTargetDesc()
1223 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1225 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
1281 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1282 assert(RC.EnumValue == EV && "Unexpected order of register classes"); in runTargetDesc()
1285 const RegSizeInfo &RI = RC.RSI.get(M); in runTargetDesc()
1289 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
1293 << RC.getName() << '\n'; in runTargetDesc()
1325 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1326 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1328 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1332 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; in runTargetDesc()
1335 RC.getSuperRegClasses(&Idx, MaskBV); in runTargetDesc()
1353 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1354 ArrayRef<CodeGenRegisterClass *> Supers = RC.getSuperClasses(); in runTargetDesc()
1360 OS << "static const TargetRegisterClass *const " << RC.getName() in runTargetDesc()
1368 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1369 if (!RC.AltOrderSelect.empty()) { in runTargetDesc()
1370 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1371 << "AltOrderSelect(const MachineFunction &MF) {" << RC.AltOrderSelect in runTargetDesc()
1373 << "static ArrayRef<MCPhysReg> " << RC.getName() in runTargetDesc()
1375 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) { in runTargetDesc()
1376 ArrayRef<Record *> Elems = RC.getOrder(oi); in runTargetDesc()
1385 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" in runTargetDesc()
1388 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) in runTargetDesc()
1389 if (RC.getOrder(oi).empty()) in runTargetDesc()
1393 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1394 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() in runTargetDesc()
1403 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1404 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1406 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " in runTargetDesc()
1407 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " in runTargetDesc()
1408 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; in runTargetDesc()
1409 printMask(OS, RC.LaneMask); in runTargetDesc()
1410 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " in runTargetDesc()
1411 << (RC.GlobalPriority ? "true" : "false") << ",\n " in runTargetDesc()
1412 << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n " in runTargetDesc()
1413 << (RC.HasDisjunctSubRegs ? "true" : "false") in runTargetDesc()
1415 << (RC.CoveredBySubRegs ? "true" : "false") in runTargetDesc()
1417 if (RC.getSuperClasses().empty()) in runTargetDesc()
1420 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1421 if (RC.AltOrderSelect.empty()) in runTargetDesc()
1424 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1433 for (const auto &RC : RegisterClasses) in runTargetDesc() local
1434 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1511 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1512 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1514 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) in runTargetDesc()
1544 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1545 OS << " {\t// " << RC.getName() << '\n'; in runTargetDesc()
1548 MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx); in runTargetDesc()
1556 OS << " " << EnumValue << ",\t// " << RC.getName() << ':' in runTargetDesc()
1582 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1583 if (RC.getBaseClassOrder()) in runTargetDesc()
1584 BaseClasses.push_back(&RC); in runTargetDesc()
1610 for (const CodeGenRegisterClass *RC : BaseClasses) { in runTargetDesc() local
1611 if (is_contained(RC->getMembers(), &Reg)) { in runTargetDesc()
1612 BaseRC = RC; in runTargetDesc()
1734 for (const CodeGenRegisterClass *RC : Category.getClasses()) in runTargetDesc() local
1735 OS << " " << RC->getQualifiedName() in runTargetDesc()
1748 for (const CodeGenRegisterClass *RC : Category.getClasses()) in runTargetDesc() local
1749 OS << " " << RC->getQualifiedName() in runTargetDesc()
1762 for (const CodeGenRegisterClass *RC : Category.getClasses()) in runTargetDesc() local
1763 OS << " " << RC->getQualifiedName() in runTargetDesc()
1831 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { in debugDump() local
1832 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1835 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
1838 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; in debugDump()
1839 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; in debugDump()
1840 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; in debugDump()
1841 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1842 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; in debugDump()
1843 OS << "\tAllocatable: " << RC.Allocatable << '\n'; in debugDump()
1844 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; in debugDump()
1845 OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n'; in debugDump()
1847 for (const CodeGenRegister *R : RC.getMembers()) { in debugDump()
1852 const BitVector &SubClasses = RC.getSubClasses(); in debugDump()
1860 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { in debugDump()