Lines Matching refs:RC
92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
93 unsigned ID = RC.getID(); in mask()
96 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); in mask()
108 << TRI.getRegClassName(&RC) << '\n'; in mask()
117 for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass, in getPhysRegBitWidth()
119 if (RC.contains(Reg)) in getPhysRegBitWidth()
120 return TRI.getRegSizeInBits(RC); in getPhysRegBitWidth()
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
124 return TRI.getRegSizeInBits(*RC); in getPhysRegBitWidth()
131 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
133 return RC; in composeWithSubRegIndex()
137 bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); in composeWithSubRegIndex()
138 bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi)); in composeWithSubRegIndex()
142 switch (RC.getID()) { in composeWithSubRegIndex()
153 dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n'; in composeWithSubRegIndex()
275 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
277 assert(RW <= RC.width()); in evaluate()
278 return eXTR(RC, 0, RW); in evaluate()
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate() argument
283 uint16_t W = RC.width(); in evaluate()
285 return eXTR(RC, W-RW, W); in evaluate()
288 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate() argument
290 assert(N*16+16 <= RC.width()); in evaluate()
291 return eXTR(RC, N*16, N*16+16); in evaluate()
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
301 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
304 return RC; in evaluate()
333 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
334 RC.fill(0, L, BT::BitValue::Zero); in evaluate()
335 return rr0(RC, Outputs); in evaluate()
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
350 RC.fill(PW, RW, BT::BitValue::Zero); in evaluate()
351 return rr0(RC, Outputs); in evaluate()
356 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
357 RC.fill(PW, RW, BT::BitValue::Zero); in evaluate()
358 return rr0(eINS(RC, eXTR(rc(1), 0, PW), 0), Outputs); in evaluate()
372 RegisterCell RC = eADD(eSXT(CW, W1), rc(2)); in evaluate() local
373 return rr0(RC, Outputs); in evaluate()
381 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate() local
382 return rr0(RC, Outputs); in evaluate()
385 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3))); in evaluate() local
386 return rr0(RC, Outputs); in evaluate()
389 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0))); in evaluate() local
390 return rr0(RC, Outputs); in evaluate()
394 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0)); in evaluate() local
395 return rr0(RC, Outputs); in evaluate()
399 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0)); in evaluate() local
400 return rr0(RC, Outputs); in evaluate()
404 RegisterCell RC = eADD(rc(1), lo(M, W0)); in evaluate() local
405 return rr0(RC, Outputs); in evaluate()
409 RegisterCell RC = eADD(rc(1), lo(M, W0)); in evaluate() local
410 return rr0(RC, Outputs); in evaluate()
414 RegisterCell RC = eADD(rc(1), lo(M, W0)); in evaluate() local
415 return rr0(RC, Outputs); in evaluate()
418 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3))); in evaluate() local
419 return rr0(RC, Outputs); in evaluate()
422 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0))); in evaluate() local
423 return rr0(RC, Outputs); in evaluate()
426 RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3))); in evaluate() local
427 return rr0(RC, Outputs); in evaluate()
430 RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3))); in evaluate() local
431 return rr0(RC, Outputs); in evaluate()
434 RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3))); in evaluate() local
435 return rr0(RC, Outputs); in evaluate()
448 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate() local
449 return rr0(RC, Outputs); in evaluate()
452 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3))); in evaluate() local
453 return rr0(RC, Outputs); in evaluate()
456 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0))); in evaluate() local
457 return rr0(RC, Outputs); in evaluate()
460 RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3))); in evaluate() local
461 return rr0(RC, Outputs); in evaluate()
483 RegisterCell RC = eADD(rc(1), lo(M, W0)); in evaluate() local
484 return rr0(RC, Outputs); in evaluate()
488 RegisterCell RC = eSUB(rc(1), lo(M, W0)); in evaluate() local
489 return rr0(RC, Outputs); in evaluate()
493 RegisterCell RC = eADD(rc(1), lo(M, W0)); in evaluate() local
494 return rr0(RC, Outputs); in evaluate()
498 RegisterCell RC = eSUB(rc(1), lo(M, W0)); in evaluate() local
499 return rr0(RC, Outputs); in evaluate()
536 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate() local
537 return rr0(RC, Outputs); in evaluate()
540 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3))); in evaluate() local
541 return rr0(RC, Outputs); in evaluate()
560 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate() local
561 return rr0(RC, Outputs); in evaluate()
564 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3))); in evaluate() local
565 return rr0(RC, Outputs); in evaluate()
573 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0))); in evaluate() local
574 return rr0(RC, Outputs); in evaluate()
577 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0))); in evaluate() local
578 return rr0(RC, Outputs); in evaluate()
646 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1); in evaluate() local
647 return rr0(eXTR(RC, 0, W0), Outputs); in evaluate()
655 RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1); in evaluate() local
656 return rr0(eXTR(RC, 0, W0), Outputs); in evaluate()
684 RegisterCell RC = rc(1); in evaluate() local
685 RC[im(2)] = BT::BitValue::Zero; in evaluate()
686 return rr0(RC, Outputs); in evaluate()
689 RegisterCell RC = rc(1); in evaluate() local
690 RC[im(2)] = BT::BitValue::One; in evaluate()
691 return rr0(RC, Outputs); in evaluate()
694 RegisterCell RC = rc(1); in evaluate() local
696 RC[BX] = RC[BX].is(0) ? BT::BitValue::One in evaluate()
697 : RC[BX].is(1) ? BT::BitValue::Zero in evaluate()
699 return rr0(RC, Outputs); in evaluate()
710 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1); in evaluate() local
711 return rr0(RC, Outputs); in evaluate()
726 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1)); in evaluate() local
728 return rr0(eZXT(RC, Wd), Outputs); in evaluate()
729 return rr0(eSXT(RC, Wd), Outputs); in evaluate()
765 RegisterCell RC = half(R2, LoH).cat(half(R1, HiH)); in evaluate() local
766 return rr0(RC, Outputs); in evaluate()
773 RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1)) in evaluate() local
775 return rr0(RC, Outputs); in evaluate()
778 RegisterCell RC = shuffle(rc(1), rc(2), 8, false); in evaluate() local
779 return rr0(RC, Outputs); in evaluate()
782 RegisterCell RC = shuffle(rc(1), rc(2), 16, false); in evaluate() local
783 return rr0(RC, Outputs); in evaluate()
786 RegisterCell RC = shuffle(rc(1), rc(2), 8, true); in evaluate() local
787 return rr0(RC, Outputs); in evaluate()
790 RegisterCell RC = shuffle(rc(1), rc(2), 16, true); in evaluate() local
791 return rr0(RC, Outputs); in evaluate()
798 RegisterCell RC(WR); in evaluate() local
802 RC.fill(i*8, i*8+8, F); in evaluate()
804 return rr0(RC, Outputs); in evaluate()
834 RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1); in evaluate() local
835 return rr0(RC, Outputs); in evaluate()
894 RegisterCell RC(W0); in evaluate() local
895 RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero)); in evaluate()
896 return rr0(RC, Outputs); in evaluate()
911 RegisterCell RC(W0); in evaluate() local
912 RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero)); in evaluate()
913 return rr0(RC, Outputs); in evaluate()
971 RegisterCell RC = RegisterCell::self(DefR, RW); in evaluate() local
972 RC.fill(PW, RW, BT::BitValue::Zero); in evaluate()
973 putCell(PD, RC, Outputs); in evaluate()