Lines Matching refs:RC
129 multiclass VLDbm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in,
132 def "" : RVM<opc, (outs RC:$vx), dag_in,
136 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
139 multiclass VLDlm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> {
140 defm "" : VLDbm<opcStr, opc, RC, dag_in>;
142 defm l : VLDbm<opcStr, opc, RC, !con(dag_in, (ins I32:$vl)), "$vl,">;
143 defm L : VLDbm<opcStr, opc, RC, !con(dag_in, (ins VLS:$vl)), "$vl,">;
147 multiclass VLDtgm<string opcStr, bits<8>opc, RegisterClass RC> {
148 defm rr : VLDlm<opcStr, opc, RC, (ins I64:$sy, I64:$sz)>;
150 defm ir : VLDlm<opcStr, opc, RC, (ins simm7:$sy, I64:$sz)>;
152 defm rz : VLDlm<opcStr, opc, RC, (ins I64:$sy, zero:$sz)>;
154 defm iz : VLDlm<opcStr, opc, RC, (ins simm7:$sy, zero:$sz)>;
156 multiclass VLDm<string opcStr, bits<8>opc, RegisterClass RC> {
157 let vc = 1 in defm "" : VLDtgm<opcStr, opc, RC>;
158 let vc = 0 in defm NC : VLDtgm<opcStr#".nc", opc, RC>;
198 multiclass VSTtgm<string opcStr, bits<8>opc, RegisterClass RC> {
199 defm rrv : VSTmm<opcStr, opc, (ins I64:$sy, I64:$sz, RC:$vx)>;
201 defm irv : VSTmm<opcStr, opc, (ins simm7:$sy, I64:$sz, RC:$vx)>;
203 defm rzv : VSTmm<opcStr, opc, (ins I64:$sy, zero:$sz, RC:$vx)>;
205 defm izv : VSTmm<opcStr, opc, (ins simm7:$sy, zero:$sz, RC:$vx)>;
207 multiclass VSTm<string opcStr, bits<8>opc, RegisterClass RC> {
208 let vc = 1, cx = 0 in defm "" : VSTtgm<opcStr, opc, RC>;
209 let vc = 0, cx = 0 in defm NC : VSTtgm<opcStr#".nc", opc, RC>;
210 let vc = 1, cx = 1 in defm OT : VSTtgm<opcStr#".ot", opc, RC>;
211 let vc = 0, cx = 1 in defm NCOT : VSTtgm<opcStr#".nc.ot", opc, RC>;
234 multiclass VGTbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
237 def "" : RVM<opc, (outs RC:$vx), dag_in,
241 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
244 multiclass VGTlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
246 defm "" : VGTbm<opcStr, argStr, opc, RC, dag_in>;
248 defm l : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
250 defm L : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
254 multiclass VGTmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
256 defm "" : VGTlm<opcStr, argStr, opc, RC, dag_in>;
258 defm m : VGTlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins VM:$m))>;
261 multiclass VGTlhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
263 defm rr : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
266 defm ir : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
269 defm rz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
272 defm iz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
275 multiclass VGTtgm<string opcStr, bits<8>opc, RegisterClass RC> {
276 let vy = ? in defm v : VGTlhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
277 let cs = 1, sw = ? in defm s : VGTlhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
279 multiclass VGTm<string opcStr, bits<8>opc, RegisterClass RC> {
280 let vc = 1 in defm "" : VGTtgm<opcStr, opc, RC>;
281 let vc = 0 in defm NC : VGTtgm<opcStr#".nc", opc, RC>;
313 multiclass VSClhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
316 !con(dag_in, (ins I64:$sy, I64:$sz, RC:$vx))>;
319 !con(dag_in, (ins simm7:$sy, I64:$sz, RC:$vx))>;
322 !con(dag_in, (ins I64:$sy, zero:$sz, RC:$vx))>;
325 !con(dag_in, (ins simm7:$sy, zero:$sz, RC:$vx))>;
327 multiclass VSCtgm<string opcStr, bits<8>opc, RegisterClass RC> {
328 let vy = ? in defm v : VSClhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
329 let cs = 1, sw = ? in defm s : VSClhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
331 multiclass VSCm<string opcStr, bits<8>opc, RegisterClass RC> {
332 let vc = 1, cx = 0 in defm "" : VSCtgm<opcStr, opc, RC>;
333 let vc = 0, cx = 0 in defm NC : VSCtgm<opcStr#".nc", opc, RC>;
334 let vc = 1, cx = 1 in defm OT : VSCtgm<opcStr#".ot", opc, RC>;
335 let vc = 0, cx = 1 in defm NCOT : VSCtgm<opcStr#".nc.ot", opc, RC>;
373 multiclass LSVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
375 def "" : RR<opc, (outs RC:$vx), dag_in, !strconcat(opcStr, " ${vx}", argStr)>;
378 def _v : RR<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
381 multiclass LSVm<string opcStr, bits<8>opc, RegisterClass RC> {
382 defm rr : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins I64:$sy, I64:$sz)>;
384 defm ir : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins uimm7:$sy, I64:$sz)>;
386 defm rm : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins I64:$sy, mimm:$sz)>;
388 defm im : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins uimm7:$sy, mimm:$sz)>;
394 multiclass LVSm<string opcStr, bits<8>opc, RegisterClass RC> {
395 def vr : RR<opc, (outs I64:$sx), (ins RC:$vx, I64:$sy),
398 def vi : RR<opc, (outs I64:$sx), (ins RC:$vx, uimm7:$sy),
442 multiclass VBRDbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
445 def "" : RV<opc, (outs RC:$vx), dag_in,
449 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
452 multiclass VBRDlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
454 defm "" : VBRDbm<opcStr, argStr, opc, RC, dag_in>;
456 defm l : VBRDbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
458 defm L : VBRDbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
462 multiclass VBRDmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
464 defm "" : VBRDlm<opcStr, argStr, opc, RC, dag_in>;
466 defm m : VBRDlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins RCM:$m))>;
469 multiclass VBRDm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
471 defm r : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins RC:$sy)>;
486 multiclass VMVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
489 def "" : RV<opc, (outs RC:$vx), dag_in,
493 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
496 multiclass VMVlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
498 defm "" : VMVbm<opcStr, argStr, opc, RC, dag_in>;
500 defm l : VMVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
502 defm L : VMVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
506 multiclass VMVmm<string opcStr, bits<8>opc, RegisterClass RC,
508 defm "" : VMVlm<opcStr, "$sy, $vz", opc, RC, dag_in>;
510 defm m : VMVlm<opcStr, "$sy, $vz, $m", opc, RC, !con(dag_in, (ins RCM:$m))>;
513 multiclass VMVm<string opcStr, bits<8>opc, RegisterClass RC,
515 defm rv : VMVmm<opcStr, opc, RC, RCM, (ins I64:$sy, RC:$vz)>;
517 defm iv : VMVmm<opcStr, opc, RC, RCM, (ins uimm7:$sy, RC:$vz)>;
527 multiclass RVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
530 def "" : RV<opc, (outs RC:$vx), dag_in,
534 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
537 multiclass RVlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
539 defm "" : RVbm<opcStr, argStr, opc, RC, dag_in>;
541 defm l : RVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
543 defm L : RVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
547 multiclass RVmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
549 defm "" : RVlm<opcStr, argStr, opc, RC, dag_in>;
551 defm m : RVlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins RCM:$m))>;
556 multiclass RVm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
561 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;
569 RegisterClass RC, RegisterClass RCM, Operand SIMM = simm7> {
573 defm vr : RVmm<opcStr, ", $vy, $sy", opc, VRC, RCM, (ins VRC:$vy, RC:$sy)>;
577 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;
585 RegisterClass RC, RegisterClass RCM> {
587 defm vv : RVmm<opcStr, ", $vy, $vz", opc, RC, RCM, (ins RC:$vy, RC:$vz)>;
589 defm rv : RVmm<opcStr, ", $sy, $vz", opc, RC, RCM, (ins ScaRC:$sy, RC:$vz)>;
591 defm mv : RVmm<opcStr, ", $sy, $vz", opc, RC, RCM, (ins mimm:$sy, RC:$vz)>;
596 multiclass RV1m<string opcStr, bits<8>opc, RegisterClass RC,
599 defm v : RVmm<opcStr, ", $vz", opc, RC, RCM, (ins RC:$vz)>;
604 multiclass RV0m<string opcStr, bits<8>opc, RegisterClass RC,
607 defm "" : RVmm<opcStr, "", opc, RC, RCM, (ins)>;
613 RegisterClass RC, RegisterClass RCM> {
615 defm vv : RVmm<opcStr, ", $vz, $vy", opc, RC, RCM, (ins RC:$vz, RC:$vy)>;
617 defm vr : RVmm<opcStr, ", $vz, $sy", opc, RC, RCM, (ins RC:$vz, ScaRC:$sy)>;
619 defm vi : RVmm<opcStr, ", $vz, $sy", opc, RC, RCM, (ins RC:$vz, uimm7:$sy)>;
624 multiclass RVSDm<string opcStr, bits<8>opc, RegisterClass RC,
627 defm vvr : RVmm<opcStr, ", ($vy, ${vz}), $sy", opc, RC, RCM,
628 (ins RC:$vy, RC:$vz, I64:$sy)>;
630 defm vvi : RVmm<opcStr, ", ($vy, ${vz}), $sy", opc, RC, RCM,
631 (ins RC:$vy, RC:$vz, uimm7:$sy)>;
636 multiclass RVSAm<string opcStr, bits<8>opc, RegisterClass RC,
639 defm vrr : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
640 (ins RC:$vz, I64:$sy, I64:$sz)>;
642 defm vrm : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
643 (ins RC:$vz, I64:$sy, mimm:$sz)>;
645 defm vir : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
646 (ins RC:$vz, uimm3:$sy, I64:$sz)>;
648 defm vim : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
649 (ins RC:$vz, uimm3:$sy, mimm:$sz)>;
654 multiclass RVF1m<string opcStr, bits<8>opc, RegisterClass RC,
657 defm v : RVmm<opcStr, ", $vy", opc, RC, RCM, (ins RC:$vy)>;
662 multiclass RVMm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
669 (ins VRC:$vy, RC:$sy, VRC:$vw)>;
675 (ins RC:$sy, VRC:$vz, VRC:$vw)>;
683 multiclass RVFIXm<string opcStr, bits<8> opc, RegisterClass RC,
686 defm v : RVmm<opcStr#"$vz", ", $vy", opc, RC, RCM, (ins RDOp:$vz, RC:$vy)>;
690 multiclass RVIbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
693 def "" : RV<opc, (outs RC:$vx), dag_in,
696 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
699 multiclass RVIlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
701 defm "" : RVIbm<opcStr, argStr, opc, RC, dag_in>;
703 defm l : RVIbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
705 defm L : RVIbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
713 RegisterClass RC> {
715 defm vr : RVIlm<opcStr, ", $vy, $sy", opc, VRC, (ins VRC:$vy, RC:$sy)>;
723 RegisterClass RC> {
726 (ins VRC:$vy, VRC:$vz, RC:$sy)>;
734 multiclass RVSHFm<string opcStr, bits<8>opc, RegisterClass RC,
736 defm vvr : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC,
737 (ins RC:$vy, RC:$vz, I64:$sy)>;
738 let cy = 0 in defm vvi : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC,
739 (ins RC:$vy, RC:$vz, SIMM:$sy)>;
763 multiclass RVMKom<string opcStr, bits<8> opc, RegisterClass RC,
766 defm v : RVMKlm<opcStr#"$vy", ", $vz", opc, RCM, (ins CCOp:$vy, RC:$vz)>;
772 multiclass RVMKm<string opcStr, bits<8> opc, RegisterClass RC,
774 defm "" : RVMKom<opcStr, opc, RC, RCM>;