| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 41 const PPCRegisterBankInfo &RBI);
72 const PPCRegisterBankInfo &RBI; member in __anone05d911e0111::PPCInstructionSelector
91 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
93 RBI(RBI), in PPCInstructionSelector()
132 const RegisterBankInfo &RBI) { in selectCopy() argument
138 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
145 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
208 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectIntToFP()
238 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectFPToInt()
245 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectZExt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anone228b8980111::ARMInstructionSelector
164 const ARMRegisterBankInfo &RBI) { in createARMInstructionSelector() argument
165 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 const ARMRegisterBankInfo &RBI) in ARMInstructionSelector() argument
176 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), in ARMInstructionSelector()
190 const RegisterBankInfo &RBI) { in guessRegClass() argument
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
215 const RegisterBankInfo &RBI) { in selectCopy() argument
220 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
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| H A D | ARMSubtarget.cpp | 109 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo()); in ARMSubtarget() local
114 InstSelector.reset(createARMInstructionSelector(TM, *this, *RBI)); in ARMSubtarget()
116 RegBankInfo.reset(RBI); in ARMSubtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kInstructionSelector.cpp | 29 const M68kRegisterBankInfo &RBI);
40 const M68kRegisterBankInfo &RBI; member in __anond52f76870111::M68kInstructionSelector
59 const M68kRegisterBankInfo &RBI) in M68kInstructionSelector() argument
61 TRI(*STI.getRegisterInfo()), RBI(RBI), in M68kInstructionSelector()
87 const M68kRegisterBankInfo &RBI) { in createM68kInstructionSelector() argument
88 return new M68kInstructionSelector(TM, Subtarget, RBI); in createM68kInstructionSelector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 36 const MipsRegisterBankInfo &RBI);
63 const MipsRegisterBankInfo &RBI; member in __anonbf07d5ca0111::MipsInstructionSelector
82 const MipsRegisterBankInfo &RBI) in MipsInstructionSelector() argument
84 RBI(RBI), in MipsInstructionSelector()
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
112 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
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| H A D | MipsSubtarget.cpp | 218 auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo()); in MipsSubtarget() local
219 RegBankInfo.reset(RBI); in MipsSubtarget()
220 InstSelector.reset(createMipsInstructionSelector(TM, *this, *RBI)); in MipsSubtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 43 const RISCVRegisterBankInfo &RBI);
121 const RISCVRegisterBankInfo &RBI; member in __anon05b3f3090111::RISCVInstructionSelector
146 const RISCVRegisterBankInfo &RBI) in RISCVInstructionSelector() argument
147 : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), in RISCVInstructionSelector()
543 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
589 if (!FMV.constrainAllUses(TII, TRI, RBI)) in select()
604 if (!PairF64.constrainAllUses(TII, TRI, RBI)) in select()
632 return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI); in select()
649 if (!SLL.constrainAllUses(TII, TRI, RBI)) in select()
655 if (!ADD.constrainAllUses(TII, TRI, RBI)) in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| H A D | X86Subtarget.cpp | 352 auto *RBI = new X86RegisterBankInfo(*getRegisterInfo()); in X86Subtarget() local
353 RegBankInfo.reset(RBI); in X86Subtarget()
354 InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI)); in X86Subtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 64 const X86RegisterBankInfo &RBI);
138 const X86RegisterBankInfo &RBI; member in __anonb75048c70111::X86InstructionSelector
157 const X86RegisterBankInfo &RBI) in X86InstructionSelector() argument
159 RBI(RBI), in X86InstructionSelector()
213 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
270 RBI.constrainGenericRegister(Reg, *RC, MRI); in selectDebugInstr()
280 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
281 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
284 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in selectCopy()
285 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 74 const AArch64RegisterBankInfo &RBI);
523 const AArch64RegisterBankInfo &RBI; member in __anonde0bbd8d0111::AArch64InstructionSelector
553 const AArch64RegisterBankInfo &RBI) in AArch64InstructionSelector() argument
555 RBI(RBI), in AArch64InstructionSelector()
768 const AArch64RegisterBankInfo &RBI, in unsupportedBinOp() argument
794 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
923 const RegisterBankInfo &RBI, Register SrcReg, in copySubReg() argument
938 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in copySubReg()
950 const RegisterBankInfo &RBI) { in getRegClassesForCopy() argument
953 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 44 const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, in AMDGPUInstructionSelector() argument
46 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
119 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
120 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
139 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
144 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
186 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
200 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
239 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
292 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
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| H A D | AMDGPURegBankCombiner.cpp | 49 const RegisterBankInfo &RBI; member in __anonc61746da0111::AMDGPURegBankCombinerImpl
119 RBI(*STI.getRegBankInfo()), TRI(*STI.getRegisterInfo()), in AMDGPURegBankCombinerImpl()
129 return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID; in isVgprRegBank()
145 MRI.setRegBank(VgprReg, RBI.getRegBank(AMDGPU::VGPRRegBankID)); in getAsVgpr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstructionSelector.cpp | 76 const RegisterBankInfo &RBI; member in __anonce99e1400111::SPIRVInstructionSelector
88 const RegisterBankInfo &RBI);
264 const RegisterBankInfo &RBI) in SPIRVInstructionSelector() argument
266 TRI(*ST.getRegisterInfo()), RBI(RBI), GR(*ST.getSPIRVGlobalRegistry()), in SPIRVInstructionSelector()
317 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
379 return MIB.constrainAllUses(TII, TRI, RBI); in spvSelect()
564 return MIB.constrainAllUses(TII, TRI, RBI); in spvSelect()
653 return MIB.constrainAllUses(TII, TRI, RBI); in selectExtInst()
668 .constrainAllUses(TII, TRI, RBI); in selectUnOpWithSrc()
703 .constrainAllUses(TII, TRI, RBI); in selectUnOp()
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| H A D | SPIRV.h | 32 const RegisterBankInfo &RBI);
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | MergedLoadStoreMotion.cpp | 322 for (BasicBlock::reverse_iterator RBI = Pred0->rbegin(), RBE = Pred0->rend(); in mergeStores() local
323 RBI != RBE;) { in mergeStores()
325 Instruction *I = &*RBI; in mergeStores()
326 ++RBI; in mergeStores()
354 RBI = Pred0->rbegin(); in mergeStores()
356 LLVM_DEBUG(dbgs() << "Search again\n"; Instruction *I = &*RBI; I->dump()); in mergeStores()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 82 RBI = MF.getSubtarget().getRegBankInfo(); in init()
83 assert(RBI && "Cannot work without RegisterBankInfo"); in init()
120 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
244 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
260 return RBI->getBreakDownCost(ValMapping, CurRegBank); in getRepairCost()
279 unsigned Cost = RBI->copyCost(*DesiredRegBank, *CurRegBank, in getRepairCost()
280 RBI->getSizeInBits(MO.getReg(), *MRI, *TRI)); in getRepairCost()
628 RBI->applyMapping(MIRBuilder, OpdMapper); in applyMapping()
645 RBI->getRegBank(MI.getOperand(1).getReg(), *MRI, *TRI); in assignInstr()
659 BestMapping = &RBI->getInstrMapping(MI); in assignInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kSubtarget.cpp | 60 auto *RBI = new M68kRegisterBankInfo(*getRegisterInfo()); in M68kSubtarget() local
61 RegBankInfo.reset(RBI); in M68kSubtarget()
62 InstSelector.reset(createM68kInstructionSelector(TM, *this, *RBI)); in M68kSubtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.cpp | 65 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo()); in PPCSubtarget() local
66 RegBankInfo.reset(RBI); in PPCSubtarget()
68 InstSelector.reset(createPPCInstructionSelector(TM, *this, *RBI)); in PPCSubtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 525 const RegisterBankInfo &RBI) const { in verify()
530 assert(RBI.getMaximumSize(RegBank->getID()) >= Length && in verify()
556 bool RegisterBankInfo::ValueMapping::verify(const RegisterBankInfo &RBI, in verify() argument
563 assert(PartMap.verify(RBI) && "Partial mapping is invalid"); in verify()
615 const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo(); in verify() local
616 (void)RBI; in verify()
638 assert(MOMapping.verify(*RBI, RBI->getSizeInBits( in verify()
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| H A D | RegisterBank.cpp | 23 bool RegisterBank::verify(const RegisterBankInfo &RBI,
44 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) && in verify()
33 verify(const RegisterBankInfo & RBI,const TargetRegisterInfo & TRI) const verify() argument
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| H A D | MachineUniformityAnalysis.cpp | 35 const auto &RBI = *F.getSubtarget().getRegBankInfo(); in markDefsDivergent() local
41 if (TRI.isUniformReg(MRI, RBI, op.getReg())) in markDefsDivergent()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 96 const RegisterBankInfo &RBI, Register Reg,
111 const RegisterBankInfo &RBI,
130 const RegisterBankInfo &RBI,
146 const RegisterBankInfo &RBI);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64Subtarget.cpp | 344 auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo()); in AArch64Subtarget() local
350 *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI)); in AArch64Subtarget()
352 RegBankInfo.reset(RBI); in AArch64Subtarget()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBank.h | 57 bool verify(const RegisterBankInfo &RBI, const TargetRegisterInfo &TRI) const;
|