| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 41 const PPCRegisterBankInfo &RBI);
72 const PPCRegisterBankInfo &RBI; member in __anone05d911e0111::PPCInstructionSelector
91 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
93 RBI(RBI), in PPCInstructionSelector()
132 const RegisterBankInfo &RBI) { in selectCopy() argument
138 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
145 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
208 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectIntToFP()
238 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectFPToInt()
245 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectZExt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/GISel/ |
| H A D | BPFInstructionSelector.cpp | 34 const BPFRegisterBankInfo &RBI);
46 const BPFRegisterBankInfo &RBI; member in __anon9e8339eb0111::BPFInstructionSelector
65 const BPFRegisterBankInfo &RBI) in BPFInstructionSelector() argument
66 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), in BPFInstructionSelector()
88 const BPFRegisterBankInfo &RBI) { in createBPFInstructionSelector() argument
89 return new BPFInstructionSelector(TM, Subtarget, RBI); in createBPFInstructionSelector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kInstructionSelector.cpp | 29 const M68kRegisterBankInfo &RBI);
40 const M68kRegisterBankInfo &RBI; member in __anond52f76870111::M68kInstructionSelector
59 const M68kRegisterBankInfo &RBI) in M68kInstructionSelector() argument
61 TRI(*STI.getRegisterInfo()), RBI(RBI), in M68kInstructionSelector()
87 const M68kRegisterBankInfo &RBI) { in createM68kInstructionSelector() argument
88 return new M68kInstructionSelector(TM, Subtarget, RBI); in createM68kInstructionSelector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anone228b8980111::ARMInstructionSelector
164 const ARMRegisterBankInfo &RBI) { in createARMInstructionSelector() argument
165 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 const ARMRegisterBankInfo &RBI) in ARMInstructionSelector() argument
176 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), in ARMInstructionSelector()
190 const RegisterBankInfo &RBI) { in guessRegClass() argument
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
215 const RegisterBankInfo &RBI) { in selectCopy() argument
220 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
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| H A D | ARMSubtarget.cpp | 108 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo()); in ARMSubtarget() local
113 InstSelector.reset(createARMInstructionSelector(TM, *this, *RBI)); in ARMSubtarget()
115 RegBankInfo.reset(RBI); in ARMSubtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 36 const MipsRegisterBankInfo &RBI);
63 const MipsRegisterBankInfo &RBI; member in __anonbf07d5ca0111::MipsInstructionSelector
82 const MipsRegisterBankInfo &RBI) in MipsInstructionSelector() argument
84 RBI(RBI), in MipsInstructionSelector()
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
112 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
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| H A D | MipsSubtarget.cpp | 221 auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo()); in MipsSubtarget() local
222 RegBankInfo.reset(RBI); in MipsSubtarget()
223 InstSelector.reset(createMipsInstructionSelector(TM, *this, *RBI)); in MipsSubtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| H A D | X86Subtarget.cpp | 359 auto *RBI = new X86RegisterBankInfo(*getRegisterInfo()); in X86Subtarget() local
360 RegBankInfo.reset(RBI); in X86Subtarget()
361 InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI)); in X86Subtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUGlobalISelUtils.cpp | 121 const RegisterBankInfo &RBI);
126 const RegisterBankInfo &RBI) { in unmergeReadAnyLane() argument
127 const RegisterBank *VgprRB = &RBI.getRegBank(AMDGPU::VGPRRegBankID); in unmergeReadAnyLane()
130 SgprDstParts.push_back(buildReadAnyLane(B, Unmerge.getReg(i), RBI)); in unmergeReadAnyLane()
135 const RegisterBankInfo &RBI) { in buildReadAnyLane() argument
137 const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID); in buildReadAnyLane()
144 unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI); in buildReadAnyLane()
150 Register VgprSrc, const RegisterBankInfo &RBI) { in buildReadAnyLane() argument
158 unmergeReadAnyLane(B, SgprDstParts, getReadAnyLaneSplitTy(Ty), VgprSrc, RBI); in buildReadAnyLane()
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| H A D | AMDGPUInstructionSelector.cpp | 44 const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, in AMDGPUInstructionSelector() argument
46 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
119 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
120 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
139 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
144 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
202 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
216 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
230 if (!constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI)) in selectCOPY_SCC_VCC()
237 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI); in selectCOPY_SCC_VCC()
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| H A D | AMDGPURegBankLegalize.cpp | 112 const RegisterBankInfo &RBI) in AMDGPURegBankLegalizeCombiner() argument
114 SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)), in AMDGPURegBankLegalizeCombiner()
115 VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)), in AMDGPURegBankLegalizeCombiner()
116 VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {}; in AMDGPURegBankLegalizeCombiner()
279 const RegisterBankInfo &RBI = *ST.getRegBankInfo(); in runOnMachineFunction() local
287 RegBankLegalizeHelper RBLHelper(B, MUI, RBI, RBLRules); in runOnMachineFunction()
361 AMDGPURegBankLegalizeCombiner Combiner(B, *ST.getRegisterInfo(), RBI); in runOnMachineFunction()
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| H A D | AMDGPURegBankSelect.cpp | 92 const SIRegisterInfo &TRI, const RegisterBankInfo &RBI) in RegBankSelectHelper() argument
94 SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)), in RegBankSelectHelper()
95 VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)), in RegBankSelectHelper()
96 VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {} in RegBankSelectHelper()
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| H A D | AMDGPURegBankLegalizeHelper.h | 33 const RegisterBankInfo &RBI; variable
78 const RegisterBankInfo &RBI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 63 const X86RegisterBankInfo &RBI);
142 const X86RegisterBankInfo &RBI; member in __anonb75048c70111::X86InstructionSelector
161 const X86RegisterBankInfo &RBI) in X86InstructionSelector() argument
163 RBI(RBI), in X86InstructionSelector()
217 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
274 RBI.constrainGenericRegister(Reg, *RC, MRI); in selectDebugInstr()
284 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
285 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
288 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in selectCopy()
289 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 74 const AArch64RegisterBankInfo &RBI);
523 const AArch64RegisterBankInfo &RBI; member in __anonde0bbd8d0111::AArch64InstructionSelector
553 const AArch64RegisterBankInfo &RBI) in AArch64InstructionSelector() argument
555 RBI(RBI), in AArch64InstructionSelector()
775 const AArch64RegisterBankInfo &RBI, in unsupportedBinOp() argument
801 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
930 const RegisterBankInfo &RBI, Register SrcReg, in copySubReg() argument
945 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in copySubReg()
957 const RegisterBankInfo &RBI) { in getRegClassesForCopy() argument
960 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 43 const RISCVRegisterBankInfo &RBI);
158 const RISCVRegisterBankInfo &RBI; member in __anon05b3f3090111::RISCVInstructionSelector
185 const RISCVRegisterBankInfo &RBI) in RISCVInstructionSelector() argument
186 : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), in RISCVInstructionSelector()
707 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in select()
753 if (!FMV.constrainAllUses(TII, TRI, RBI)) in select()
768 if (!PairF64.constrainAllUses(TII, TRI, RBI)) in select()
795 return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI); in select()
800 return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); in select()
840 if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI)) in selectUnmergeValues()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstructionSelector.cpp | 66 const RegisterBankInfo &RBI; member in __anonce99e1400111::SPIRVInstructionSelector
79 const RegisterBankInfo &RBI);
360 const RegisterBankInfo &RBI) in SPIRVInstructionSelector() argument
362 TRI(*ST.getRegisterInfo()), RBI(RBI), GR(*ST.getSPIRVGlobalRegistry()), in SPIRVInstructionSelector()
533 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
591 .constrainAllUses(TII, TRI, RBI); in BuildCOPY()
633 return MIB.constrainAllUses(TII, TRI, RBI); in spvSelect()
869 return MIB.constrainAllUses(TII, TRI, RBI) && in spvSelect()
878 .constrainAllUses(TII, TRI, RBI); in spvSelect()
887 .constrainAllUses(TII, TRI, RBI); in spvSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | MergedLoadStoreMotion.cpp | 324 for (BasicBlock::reverse_iterator RBI = Pred0->rbegin(), RBE = Pred0->rend(); in mergeStores() local
325 RBI != RBE;) { in mergeStores()
327 Instruction *I = &*RBI; in mergeStores()
328 ++RBI; in mergeStores()
356 RBI = Pred0->rbegin(); in mergeStores()
358 LLVM_DEBUG(dbgs() << "Search again\n"; Instruction *I = &*RBI; I->dump()); in mergeStores()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFSubtarget.cpp | 112 auto *RBI = new BPFRegisterBankInfo(*getRegisterInfo()); in BPFSubtarget() local
113 RegBankInfo.reset(RBI); in BPFSubtarget()
116 *static_cast<const BPFTargetMachine *>(&TM), *this, *RBI)); in BPFSubtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 82 RBI = MF.getSubtarget().getRegBankInfo(); in init()
83 assert(RBI && "Cannot work without RegisterBankInfo"); in init()
120 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
244 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
260 return RBI->getBreakDownCost(ValMapping, CurRegBank); in getRepairCost()
279 unsigned Cost = RBI->copyCost(*DesiredRegBank, *CurRegBank, in getRepairCost()
280 RBI->getSizeInBits(MO.getReg(), *MRI, *TRI)); in getRepairCost()
628 RBI->applyMapping(MIRBuilder, OpdMapper); in applyMapping()
645 RBI->getRegBank(MI.getOperand(1).getReg(), *MRI, *TRI); in assignInstr()
659 BestMapping = &RBI->getInstrMapping(MI); in assignInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kSubtarget.cpp | 61 auto *RBI = new M68kRegisterBankInfo(*getRegisterInfo()); in M68kSubtarget() local
62 RegBankInfo.reset(RBI); in M68kSubtarget()
63 InstSelector.reset(createM68kInstructionSelector(TM, *this, *RBI)); in M68kSubtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.cpp | 67 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo()); in PPCSubtarget() local
68 RegBankInfo.reset(RBI); in PPCSubtarget()
70 InstSelector.reset(createPPCInstructionSelector(TM, *this, *RBI)); in PPCSubtarget()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 523 const RegisterBankInfo &RBI) const { in verify()
528 assert(RBI.getMaximumSize(RegBank->getID()) >= Length && in verify()
554 bool RegisterBankInfo::ValueMapping::verify(const RegisterBankInfo &RBI, in verify() argument
561 assert(PartMap.verify(RBI) && "Partial mapping is invalid"); in verify()
613 const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo(); in verify() local
614 (void)RBI; in verify()
636 assert(MOMapping.verify(*RBI, RBI->getSizeInBits( in verify()
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| H A D | RegisterBank.cpp | 23 bool RegisterBank::verify(const RegisterBankInfo &RBI,
44 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) && in verify()
33 verify(const RegisterBankInfo & RBI,const TargetRegisterInfo & TRI) const verify() argument
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