xref: /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/SPIRV.h (revision 0fca6ea1d4eea4c934cfff25ac9ee8ad6fe95583)
181ad6265SDimitry Andric //===-- SPIRV.h - Top-level interface for SPIR-V representation -*- C++ -*-===//
281ad6265SDimitry Andric //
381ad6265SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
481ad6265SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
581ad6265SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
681ad6265SDimitry Andric //
781ad6265SDimitry Andric //===----------------------------------------------------------------------===//
881ad6265SDimitry Andric 
981ad6265SDimitry Andric #ifndef LLVM_LIB_TARGET_SPIRV_SPIRV_H
1081ad6265SDimitry Andric #define LLVM_LIB_TARGET_SPIRV_SPIRV_H
1181ad6265SDimitry Andric 
1281ad6265SDimitry Andric #include "MCTargetDesc/SPIRVMCTargetDesc.h"
1381ad6265SDimitry Andric #include "llvm/CodeGen/MachineFunctionPass.h"
1481ad6265SDimitry Andric #include "llvm/Target/TargetMachine.h"
1581ad6265SDimitry Andric 
1681ad6265SDimitry Andric namespace llvm {
1781ad6265SDimitry Andric class SPIRVTargetMachine;
1881ad6265SDimitry Andric class SPIRVSubtarget;
1981ad6265SDimitry Andric class InstructionSelector;
2081ad6265SDimitry Andric class RegisterBankInfo;
2181ad6265SDimitry Andric 
225f757f3fSDimitry Andric ModulePass *createSPIRVPrepareFunctionsPass(const SPIRVTargetMachine &TM);
23*0fca6ea1SDimitry Andric FunctionPass *createSPIRVMergeRegionExitTargetsPass();
247a6dacacSDimitry Andric FunctionPass *createSPIRVStripConvergenceIntrinsicsPass();
25bdd1243dSDimitry Andric FunctionPass *createSPIRVRegularizerPass();
2681ad6265SDimitry Andric FunctionPass *createSPIRVPreLegalizerPass();
27*0fca6ea1SDimitry Andric FunctionPass *createSPIRVPostLegalizerPass();
28*0fca6ea1SDimitry Andric ModulePass *createSPIRVEmitIntrinsicsPass(SPIRVTargetMachine *TM);
2981ad6265SDimitry Andric InstructionSelector *
3081ad6265SDimitry Andric createSPIRVInstructionSelector(const SPIRVTargetMachine &TM,
3181ad6265SDimitry Andric                                const SPIRVSubtarget &Subtarget,
3281ad6265SDimitry Andric                                const RegisterBankInfo &RBI);
3381ad6265SDimitry Andric 
3481ad6265SDimitry Andric void initializeSPIRVModuleAnalysisPass(PassRegistry &);
35*0fca6ea1SDimitry Andric void initializeSPIRVConvergenceRegionAnalysisWrapperPassPass(PassRegistry &);
3681ad6265SDimitry Andric void initializeSPIRVPreLegalizerPass(PassRegistry &);
37*0fca6ea1SDimitry Andric void initializeSPIRVPostLegalizerPass(PassRegistry &);
3881ad6265SDimitry Andric void initializeSPIRVEmitIntrinsicsPass(PassRegistry &);
3981ad6265SDimitry Andric } // namespace llvm
4081ad6265SDimitry Andric 
4181ad6265SDimitry Andric #endif // LLVM_LIB_TARGET_SPIRV_SPIRV_H
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