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Searched refs:R11 (Results 1 – 25 of 84) sorted by relevance

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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath_dlib_asm.S77 #define minmin R11:10 // exactly 0x800000000000000000LL
78 #define minminh R11
212 #define minmin R11:10 // exactly 0x800000000000000000LL
213 #define minminh R11
331 #define lmantc R11:10
332 #define mantch R11
H A Dfastmath2_dlib_asm.S70 #define minmin R11:10 // exactly 0x000000000000008001LL
171 #define minmin R11:10 // exactly 0x000000000000008001LL
269 #define lmantc R11:10
271 #define guard R11
H A Dfastmath2_ldlib_asm.S264 #define lmantc R11:10
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td36 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
50 R11)>;
56 R11, CP, DP, SP, LR)> {
H A DXCoreCallingConv.td30 // The 'nest' parameter, if any, is passed in R11.
31 CCIfNest<CCAssignToReg<[R11]>>,
H A DXCoreInstrInfo.td629 let Uses = [R11], isCall=1 in
643 let Defs = [R11], hasSideEffects = 0, isReMaterializable = 1 in
647 let Defs = [R11], isReMaterializable = 1 in
649 [(set R11, (cprelwrapper tglobaladdr:$a))]>;
651 let Defs = [R11] in
676 let Defs = [R11], isReMaterializable = 1 in {
681 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
690 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
694 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
699 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td36 def RR2 : LanaiReg<11, "rr2", [R11]>, DwarfRegAlias<R11>;
50 R10, RR1, R11, RR2, // programmer controlled registers
H A DLanaiRegisterInfo.cpp56 Reserved.set(Lanai::R11); in getReservedRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
275 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
289 R11, R10, R9, R8,
294 LR, R11)>;
304 // When enforcing an AAPCS compliant frame chain, R11 is used as the frame
308 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R11,
317 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
344 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
363 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
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H A DARMBaseRegisterInfo.h54 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
66 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
94 case R11: case LR: in isSplitFPArea2Register()
H A DARMSLSHardening.cpp145 {"__llvm_slsblr_thunk_arm_r11", ARM::R11, false},
159 {"__llvm_slsblr_thunk_thumb_r11", ARM::R11, true},
H A DThumb1FrameLowering.cpp215 case ARM::R11: in emitPrologue()
366 case ARM::R11: in emitPrologue()
400 case ARM::R11: in emitPrologue()
835 ARM::R10, ARM::R11};
/freebsd/crypto/openssl/crypto/sha/asm/
H A Dkeccak1600-avx512vl.pl56 my ($R20,$R01,$R31,$R21,$R41,$R11) = map("%ymm$_",(16..21));
110 vprolvq $R11,$A11,@T[1] # $A11 -> future $A01
215 vmovdqa64 5*32(%r8),$R11
301 vmovdqa64 5*32(%r8),$R11
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IndirectThunks.cpp102 BuildMI(&MF.front(), DebugLoc(), TII->get(X86::JMP64r)).addReg(X86::R11); in populateThunk()
103 MF.front().addLiveIn(X86::R11); in populateThunk()
150 ThunkReg = X86::R11; in populateThunk()
H A DX86RegisterInfo.td294 def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;
586 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, R16, R17,
590 // GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
598 def GR64_ArgRef: RegisterClass<"X86", [i64], 64, (add R10, R11)> {
632 R8, R9, R11, RIP, RSP)>;
634 R8, R9, R10, R11,
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td47 def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>;
90 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
105 def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td66 def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>, DwarfRegNum<[11]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h69 case Lanai::R11: in getLanaiRegisterNumbering()
/freebsd/contrib/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_unwind_win.cpp76 stack_frame.AddrFrame.Offset = ctx.R11; in UnwindSlow()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td49 R11, // Stack Ptr
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCTargetDesc.cpp44 InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */); in createBPFMCRegisterInfo()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp239 Value *R11, *R12; in getMaskedTypeForICmpPair() local
241 if (decomposeBitTestICmp(R1, R2, PredR, R11, R12, R2)) { in getMaskedTypeForICmpPair()
242 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
243 A = R11; in getMaskedTypeForICmpPair()
247 D = R11; in getMaskedTypeForICmpPair()
255 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) { in getMaskedTypeForICmpPair()
258 R11 = R1; in getMaskedTypeForICmpPair()
262 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
263 A = R11; in getMaskedTypeForICmpPair()
269 D = R11; in getMaskedTypeForICmpPair()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.h275 return IsPPC64 ? PPC::X11 : PPC::R11; in getEnvironmentPointerRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp98 BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11};

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