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Searched refs:PredReg (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp172 ARMCC::CondCodes Pred, unsigned PredReg);
176 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
182 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
487 unsigned PredReg) { in UpdateBaseRegUses() argument
556 .addReg(PredReg); in UpdateBaseRegUses()
578 .addReg(PredReg); in UpdateBaseRegUses()
628 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti() argument
748 .add(predOps(Pred, PredReg)); in CreateLoadStoreMulti()
759 .add(predOps(Pred, PredReg)); in CreateLoadStoreMulti()
765 .add(predOps(Pred, PredReg)); in CreateLoadStoreMulti()
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H A DThumb2InstrInfo.h82 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
88 Register &PredReg);
90 Register PredReg; in getVPTInstrPredicate() local
91 return getVPTInstrPredicate(MI, PredReg); in getVPTInstrPredicate()
H A DThumb2InstrInfo.cpp73 Register PredReg; in ReplaceTailWithBranchTo() local
74 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo()
121 Register PredReg; in isLegalToSplitMBBAt() local
122 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
315 ARMCC::CondCodes Pred, Register PredReg, in emitT2RegPlusImmediate() argument
321 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
338 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
345 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
354 .add(predOps(Pred, PredReg)) in emitT2RegPlusImmediate()
366 .add(predOps(Pred, PredReg)) in emitT2RegPlusImmediate()
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H A DMVEVPTBlockPass.cpp101 Register PredReg; in StepOverPredicatedInstrs() local
111 NextPred = getVPTInstrPredicate(*Iter, PredReg); in StepOverPredicatedInstrs()
247 Register PredReg; in InsertVPTBlocks() local
250 ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg); in InsertVPTBlocks()
H A DThumb2SizeReduction.cpp466 Register PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
479 .addReg(PredReg) in ReduceLoadStore()
684 Register PredReg; in ReduceSpecial() local
685 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
726 Register PredReg; in ReduceSpecial() local
728 if (getInstrPredicate(*MI, PredReg) != ARMCC::AL) in ReduceSpecial()
800 Register PredReg; in ReduceTo2Addr() local
801 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceTo2Addr()
892 Register PredReg; in ReduceToNarrow() local
893 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceToNarrow()
H A DThumbRegisterInfo.cpp63 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool() argument
75 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitThumb1LoadConstPool()
83 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool() argument
104 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
111 PredReg, MIFlags); in emitLoadConstPool()
114 PredReg, MIFlags); in emitLoadConstPool()
H A DMLxExpansionPass.cpp282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
295 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
307 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
H A DThumbRegisterInfo.h43 Register PredReg = Register(),
H A DThumb2ITBlockPass.cpp197 Register PredReg; in InsertITInstructions() local
198 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in InsertITInstructions()
H A DARMBaseInstrInfo.h541 unsigned PredReg = 0) {
543 MachineOperand::CreateReg(PredReg, false)}};
782 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
798 ARMCC::CondCodes Pred, Register PredReg,
805 ARMCC::CondCodes Pred, Register PredReg,
H A DARMBaseRegisterInfo.cpp528 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
540 .add(predOps(Pred, PredReg)) in emitLoadConstPool()
881 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
894 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
898 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
H A DARMBaseRegisterInfo.h139 Register PredReg = Register(),
H A DARMConstantIslandPass.cpp1451 Register PredReg; in createNewWater() local
1454 getITInstrPredicate(*I, PredReg) != ARMCC::AL; in createNewWater()
1497 Register PredReg; in createNewWater() local
1498 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in createNewWater()
1521 Register PredReg; in createNewWater() local
1522 assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL); in createNewWater()
1924 Register PredReg; in optimizeThumb2Branches() local
1926 ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg); in optimizeThumb2Branches()
H A DARMFrameLowering.cpp677 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate() argument
680 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
683 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
691 unsigned PredReg = 0) { in emitSPUpdate() argument
693 MIFlags, Pred, PredReg); in emitSPUpdate()
3181 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr() local
3200 Pred, PredReg); in eliminateCallFramePseudoInstr()
3204 Pred, PredReg); in eliminateCallFramePseudoInstr()
3211 MachineInstr::NoFlags, Pred, PredReg); in eliminateCallFramePseudoInstr()
H A DARMISelDAGToDAG.cpp1749 SDValue PredReg; in tryMVEIndexedLoad() local
1767 PredReg = CurDAG->getRegister(0, MVT::i32); in tryMVEIndexedLoad()
1783 PredReg = LD->getMask(); in tryMVEIndexedLoad()
1830 PredReg, in tryMVEIndexedLoad()
2916 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in SelectCDE_CXxD() local
2918 Ops.push_back(PredReg); in SelectCDE_CXxD()
4258 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4259 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg}; in Select()
4270 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4271 SDValue Ops[] = {N->getOperand(0), N->getOperand(1), Pred, PredReg}; in Select()
[all …]
H A DARMBaseInstrInfo.cpp2077 Register &PredReg) { in getInstrPredicate() argument
2080 PredReg = 0; in getInstrPredicate()
2084 PredReg = MI.getOperand(PIdx+1).getReg(); in getInstrPredicate()
2107 Register PredReg; in commuteInstructionImpl() local
2108 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
2110 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
2315 ARMCC::CondCodes Pred, Register PredReg, in emitARMRegPlusImmediate() argument
2321 .add(predOps(Pred, PredReg)) in emitARMRegPlusImmediate()
2345 .add(predOps(Pred, PredReg)) in emitARMRegPlusImmediate()
5465 Register PredReg; in findCMPToFoldIntoCBZ() local
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H A DARMExpandPseudoInsts.cpp1062 Register PredReg; in ExpandMOV32BitImm() local
1063 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ExpandMOV32BitImm()
1105 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
1106 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
1130 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
1144 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp177 MCRegister PredReg = Predicate.getReg(); in getCompoundOp() local
179 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || in getCompoundOp()
180 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3)); in getCompoundOp()
187 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; in getCompoundOp()
189 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; in getCompoundOp()
191 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; in getCompoundOp()
193 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t; in getCompoundOp()
H A DHexagonMCChecker.cpp69 MCRegister &PredReg, bool &isTrue) { in initReg() argument
73 PredReg = R; in initReg()
78 NewPreds.insert(PredReg); in initReg()
94 MCRegister PredReg; in init() local
100 initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue); in init()
102 initReg(MCI, ImpUse, PredReg, isTrue); in init()
131 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
182 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
H A DHexagonMCChecker.h80 void initReg(MCInst const &, MCRegister, MCRegister &PredReg, bool &isTrue);
H A DHexagonMCDuplexInfo.cpp190 MCRegister DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
473 PredReg = MCI.getOperand(1).getReg(); // P0 in getDuplexCandidateGroup()
475 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) { in getDuplexCandidateGroup()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp96 bool isScalarPred(RegSubRegPair PredReg);
298 bool HexagonGenPredicate::isScalarPred(RegSubRegPair PredReg) { in isScalarPred() argument
300 WorkQ.push(PredReg); in isScalarPred()
H A DHexagonInstrInfo.h435 bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const;
469 bool getPredReg(ArrayRef<MachineOperand> Cond, Register &PredReg,
H A DHexagonInstrInfo.cpp1704 Register PredReg; in PredicateInstruction() local
1706 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags); in PredicateInstruction()
1709 T.addReg(PredReg, PredRegFlags); in PredicateInstruction()
1723 MRI.clearKillFlags(PredReg); in PredicateInstruction()
3234 Register PredReg) const { in predCanBeUsedAsDotNew()
3237 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg)) in predCanBeUsedAsDotNew()
3239 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg)) in predCanBeUsedAsDotNew()
4554 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg() argument
4562 PredReg = Cond[1].getReg(); in getPredReg()
H A DHexagonHardwareLoops.cpp644 Register PredReg; in getLoopTripCount() local
646 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) in getLoopTripCount()
648 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()

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