175                            ARMCC::CondCodes Pred, unsigned PredReg);
179         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
185         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
490                                         unsigned PredReg) {  in UpdateBaseRegUses()  argument
559           .addReg(PredReg);  in UpdateBaseRegUses()
581         .addReg(PredReg);  in UpdateBaseRegUses()
631     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreMulti()  argument
751               .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
762             .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
768             .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
773           .add(predOps(Pred, PredReg))  in CreateLoadStoreMulti()
818       UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);  in CreateLoadStoreMulti()
825   MIB.addImm(Pred).addReg(PredReg);  in CreateLoadStoreMulti()
838     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreDouble()  argument
855   MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in CreateLoadStoreDouble()
908   Register PredReg;  in MergeOpsUpdate()  local
909   ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);  in MergeOpsUpdate()
914                                    Opcode, Pred, PredReg, DL, Regs,  in MergeOpsUpdate()
918                                   Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);  in MergeOpsUpdate()
1192                                   ARMCC::CondCodes Pred, Register PredReg) {  in isIncrementOrDecrement()  argument
1213       MIPredReg != PredReg)  in isIncrementOrDecrement()
1224                  ARMCC::CondCodes Pred, Register PredReg, int &Offset) {  in findIncDecBefore()  argument
1237   Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);  in findIncDecBefore()
1244                 ARMCC::CondCodes Pred, Register PredReg, int &Offset,  in findIncDecAfter()  argument
1257     unsigned Off = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);  in findIncDecAfter()
1297   Register PredReg;  in MergeBaseUpdateLSMultiple()  local
1298   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLSMultiple()
1313     = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLSMultiple()
1320     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);  in MergeBaseUpdateLSMultiple()
1353     .addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLSMultiple()
1493   Register PredReg;  in MergeBaseUpdateLoadStore()  local
1494   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLoadStore()
1500     = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLoadStore()
1507     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);  in MergeBaseUpdateLoadStore()
1535                    .addReg(PredReg)  in MergeBaseUpdateLoadStore()
1551                 .addReg(PredReg)  in MergeBaseUpdateLoadStore()
1563                 .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1575               .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1593                      .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1603                      .add(predOps(Pred, PredReg))  in MergeBaseUpdateLoadStore()
1631   Register PredReg;  in MergeBaseUpdateLSDouble()  local
1632   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);  in MergeBaseUpdateLSDouble()
1637                                                             PredReg, Offset);  in MergeBaseUpdateLSDouble()
1642     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);  in MergeBaseUpdateLSDouble()
1661      .addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLSDouble()
1738                           unsigned PredReg, const TargetInstrInfo *TII,  in InsertLDR_STR()  argument
1745     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1754     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1801   Register PredReg;  in FixInvalidRegPairOp()  local
1802   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in FixInvalidRegPairOp()
1813         .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1821         .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1844                     false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI);  in FixInvalidRegPairOp()
1846                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1860                     EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1863                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1901       Register PredReg;  in LoadStoreMultipleOpti()  local
1902       ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);  in LoadStoreMultipleOpti()
2172                           Register &BaseReg, int &Offset, Register &PredReg,
2258     Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) {  in CanFormLdStDWord()  argument
2318   Pred = getInstrPredicate(*Op0, PredReg);  in CanFormLdStDWord()
2417         Register BaseReg, PredReg;  in RescheduleOps()  local
2425                                              Offset, PredReg, Pred, isT2)) {  in RescheduleOps()
2445             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
2459             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
2566       Register PredReg;  in RescheduleLoadStoreInstrs()  local
2567       if (getInstrPredicate(MI, PredReg) != ARMCC::AL)  in RescheduleLoadStoreInstrs()
3180     Register PredReg;  in DistributeIncrements()  local
3182         getInstrPredicate(*Increment, PredReg) != ARMCC::AL)  in DistributeIncrements()